TNETA1570 datasheet(34/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

transmit completion rings with/without interrupt (continued)

ENTRY

DESCRIPTION

Word 0

Control, buffer pointer

The definitions of the fields are as follows:

word 0

OWN (bit 31)

ABORT (bit 30)

Pointer (bits 29 − 0)

OWN (bit 31)

This bit is set by the host indicating that the entry is available for use by the TNETA1570. This bit is cleared by

the TNETA1570 indicating that the entry is owned by the host. If the OWN bit is not set when the TNETA1570

attempts to post an entry, TX freeze occurs.

ABORT (bit 30)

This bit is set by the TNETA1570 indicating that segmentation of the packet was aborted due to the ABORT bit

being set in the transmit-descriptor entry.

address (bits 29 −0)

This field contains the upper 30 bits of the buffer address that has completed segmentation. The lower two bits

are always zero because the buffer is aligned to a 32-bit boundary.

high-priority-segmentation service

The TNETA1570 provides a high-priority-segmentation service that bypasses the scheduler table and the

normal segmentation flow. This method can be used to insert constant bit-rate traffic into the transmit data

stream by using a method other than the scheduler table. The operation of the high-priority-segmentation

service requires the use of two external pins, the high-priority-segmentation request (HPSREQ) input and the

high-priority-segmentation acknowledge (HPSACK) output.

HPSREQ is sampled by the TNETA1570 at each new segmentation opportunity, synchronous to the PCI-bus

clock. When the input is active, the TNETA1570 initiates the procedure for transmitting a cell from TX DMA

channel 1.

NOTE: This method requires that transmit DMA channel 1 not be used for any other data traffic and that the

number 1 does not appear in the scheduler table.

Normal scheduler table look-up and pointer-increment processing is suspended until the next segmentation

opportunity for a new cell. HPSACK is asserted for one PCI-bus-clock cycle. HPSREQ must be deasserted

within two PCI-bus-clock cycles of HPSACK being asserted to ensure that another cell is not segmented for TX

DMA channel 1. If HPSREQ is not deasserted within two PCI-bus clock cycles of HPSACK being asserted,

another cell is sent from TX DMA channel 1. To ensure that the high-priority-segmentation request is processed,

HPSREQ must remain active until HPSACK is set low.

ATM header-error-check (HEC) byte generation

The TNETA1570 generates the HEC byte in the 5-byte ATM header on all outgoing ATM cells in accordance

with the appropriate specifications (ANSI T1.624, CCIFT 1.432, and ATM Forum UNI specification version 3.0).

To facilitate testing and functional verification, a mechanism to error the HEC byte in the outgoing cells is made

available in the configuration register. When the HEC bit in the configuration register is set, the HEC byte is

inverted prior to insertion into the outgoing cell.

TNETA1570 数据表(PDF) 34 Page - Texas Instruments

TNETA1570 数据表(HTML) 34 Page - Texas Instruments

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