TNETA1570 datasheet(30/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

word 4

Start-of-Next-Buffer Address (bits 31 − 0)

This field contains the address of the next buffer in the transmit buffer chain to be segmented. The buffer is either

32 bit or 64 bit aligned. This word is copied from word 1 of the descriptor entry and shifted left two bits to form

a complete 32-bit address.

word 5

Start-of-Next-Buffer Address (bits 31 − 0)

This field is copied from word 4 prior to the start of segmentation and provides a place holder for the entry written

in the transmit completion ring. The transmit completion ring is updated when the segmentation of a buffer is

complete.

word 6

Partial-AAL5 Transmit CRC (bits 31 − 0)

This field is used by the TNETA1570 to hold the interim AAL5-packet CRC calculation.

word 7

AAL5-Control Field (bits 31 − 16)

AAL5-Length Field (bits 15 − 0)

The AAL5-control field is copied directly from word 3 of the descriptor entry. The AAL5-length field must be

immediately calculated by the TNETA1570 because segmentation can begin before all of the packet is in

memory.

transmit packet-segmentation rings

Addressing

In host memory. The entries are addressed using the TX DMA state-table entry.

Number of rings supported

One ring per TX DMA channel (i.e., max = 1024)

Size: set in the TX packet-

segmentation ring-size register

Max logical entries: 256

Max 32-bit words:

256

Min logical entries: 1

Min 32-bit words:

The transmit packet-segmentation rings are located in host memory and provide the address of the first buffer

of the next packet to be segmented. Each transmit DMA channel has its own packet-segmentation ring. The

size of the rings is programmable through the transmit packet-segmentation ring-size register, up to a maximum

of 256 entries per ring. The structure of a packet-segmentation ring is shown below:

ENTRY

DESCRIPTION

Word 0

Control, buffer pointer

The definitions of the fields are as follows:

word 0

OWN (bit 31)

Reserved (bit 30)

Pointer (bits 29 − 0)

TNETA1570 数据表(PDF) 30 Page - Texas Instruments

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