TNETA1570 datasheet(31/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

OWN (bit 31)

This bit is set by the host indicating that the first buffer of a packet is ready for segmentation. This bit and the

rest of the 32-bit word is cleared by the TNETA1570 after segmentation of the packet is complete indicating that

the entry is available for use by the host.

pointer (bits 29 −0)

This field is set by the host and contains the upper 30 bits of the 32-bit address of the first buffer of a packet

that is ready for segmentation. The lower two address bits are always set to zero because the data buffers are

aligned to a 32-bit boundary. These bits and the OWN bit are cleared by the TNETA1570 after segmentation

of the packet is complete indicating that the entry is available for use by the host.

transmit data buffers

Addressing

First buffer in new packets: address stored in transmit packet-segmentation ring

New buffer in on-going packet: address stored in previous buffer descriptor

On-going buffer: address stored in TX DMA state table

Size

Min size: buffer descriptor + 1-byte payload data

Max size: buffer descriptor + 65535-byte payload data

Packets (buffer

chains) supported

Max number of packets simultaneously on-going segmentation: 1023

Max number of queued new packets on one transmit packet-segmentation ring: 256

Max total number of queued new packets: 256 x 256 = 65536

The descriptor entry and the user data are both placed into the data buffer (located in host memory) for

segmentation. The descriptor entry consists of four 32-bit words followed by the user data. The buffer size of

the user data is user programmable from 1 byte to 64K bytes using the data-byte-count field in the buffer

descriptor. The size is programmable on a per-DMA-channel basis. The total transmit data buffer must be at

least five (4 plus 1) words and contain at least one byte of data. The maximum total size is 16388 ( 4 plus 16384)

words and contain 65535 bytes of data.

Descriptor Entry

(four 32-bit words)

User Information

The descriptor entry contains four 32-bit words as described below:

ENTRY

DESCRIPTION

Word 0

Control field, buffer offset, buffer data-byte count

Word 1

Start-of-next-buffer pointer

Word 2

4-byte ATM header

Word 3

PCS-UU/CPI field (AAL5 control field)

NOTE: A possible race condition can occur when updating the descriptor field, unless the OWN bit is in the last

field to be updated in the descriptor field. The race occurs if the OWN bit gets updated and then the write

operation is discontinued by the PCI bus before the complete descriptor has been updated.

The definitions of the fields inside each word follow:

word 0

Control (bits 31 − 25)

Reserved (bit 24)

Buffer Offset (bits 23 − 16)

Buffer-Data-Byte Count (bits 15 − 0)

TNETA1570 数据表(PDF) 31 Page - Texas Instruments

TNETA1570 数据表(HTML) 31 Page - Texas Instruments

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