TNETA1570 datasheet(59/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

internal registers and counters (continued)

DESCRIPTION

TX Packet-Segmentation Ring-Size

FIFO Free-Buffer-Size Register

001Ch

HEC-Error Counter

AAL5 CPCS PDU Discard Register

0020h

Unknown-Protocols Counter

0024h

ATM-Cells-Received Counter

0028h

ATM-Cells-Transmitted Counter

002ch

VCI-Mask Register

TX FIFO Maximum Occupancy Value

RX FIFO Maximum Occupancy Value

0030h

Reserved

Scheduler-Table-Size Register

0034h

Software Reset

0038h

TX Completion Ring Without Interrupt-Pointer Address

0200h

TX Completion Ring With Interrupt-Pointer Address

0204h

RX Completion Ring Without Interrupt-Pointer Address

0208h

RX Completion Ring With Interrupt-Pointer Address

020Ch

configuration register

This register is used to program the operation of the device. This register is accessed as a 32-bit word, although

not all 32 bits are used. The register is read/write and is cleared when a hardware or software reset occurs.

RESERVED

NNI/

UNI

MAX_RETRY

_COUNT

LOOP_

BACK

TX_HEC

_ERR

SMALL_MAP

EN_TX

EN_RX

ENDN_SEL

BP_SEL

EN_RAT

bits 31 − 14

bit 13

bits 12 − 9

bit 8

bit 7

bit 6

bit 5

bit 4

bits 3 − 2

bit 1

bit 0

NNI/UNI (bit 13) − select NNI or UNI ATM-cell-header interpretation

When this bit is not set (= 0) the ATM cell header is interpreted as NNI ATM cell header, (i.e., the first four bits

in the header are used as part of the VPI value). When this bit is set (= 1), the cell header is interpreted as UNI

cell header, (i.e., the first four bits are considered GFC bits and masked before the VPI field is used as an

address to the RX VPI/VCI DMA pointer table). The GFC bits are not used in the TNETA1570, but they are

passed on to the host as part of the ATM header in the RX data buffers. The NNI/UNI bit is cleared (= 0) after

reset.

MAX_RETRY_COUNT (bits 12 −9)

These bits specify the maximum number of retries that the TNETA1570 master attempts for any transaction

before asserting PSERR. If this field is set to 0, the master retries forever. Reset value is zero.

LOOP_BACK (bit 8)

If the LOOP_BACK bit is set, the segmented data is looped back into the reassembly engine. External data

available for reassembly are ignored. No loopback is performed if the bit is not set.

TX_HEC_ERR (bit 7)

The HEC field of a segmented package is inverted if the TX_HE_ ER bit is set high. The HEC field is transmitted

correctly if the bit is not set.

TNETA1570 数据表(PDF) 59 Page - Texas Instruments

TNETA1570 数据表(HTML) 59 Page - Texas Instruments

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