TNETA1570 datasheet(52/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

device command and status registers

The system software accesses the status and command registers for error recovery, diagnostic, and control

purposes. The command register is provided to enable coarse control over a device’s ability to generate and

respond to PCI cycles. The command register bits are defined in the following table.

BIT

NAME

I/O FUNCTION

RESET

VALUE

I/O Space

This bit enables the device to respond to I/O accesses within its address space. The TNETA1570

does not support I/O mapped accesses; therefore, this bit is hardwired to a 0.

Memory space

This bit enables the device to respond to memory accesses within its address space. If this bit

is cleared, the TNETA1570 does not respond to memory-mapped accesses.

Bus master

This bit enables the device to act as a PCI-bus master. If this bit is cleared, the device does not

act as a master on the PCI bus.

Special cycles

This bit controls the device’s response to special-cycle commands. If this bit Is cleared, the

device ignores all special-cycle commands. If this bit is set to 1, the device can monitor

special-cycle commands.

Memory write and

invalidate enable

This bit enables the device to use the memory-write and invalidate command. The TNETA1570

does not support the memory-write and invalidate command as a master; therefore, this bit is

hardwired to a 0.

VGA-palette snoop

This bit is not applicable for the TNETA1570 and is hardwired to a 0.

Parity-error response

This bit controls whether the device responds to detected parity errors. If this bit is set, the

TNETA1570 responds normally to parity errors. If this bit is cleared, the TNETA1570 ignores

detected parity errors.

Wait-cycle control

This bit indicates whether the device performs address stepping. The TNETA1570 does not

require address stepping; therefore, this bit is hardwired to 0.

SERR enable

This bit is an enable for the output driver on SERR. If this bit is cleared and a system-error

condition is set inside the TNETA1570, the error signal does not appear on the external SERR

signal.

Fast back-to-back

enable

This bit controls whether the device is allowed to perform back-to-back writes to different targets.

The TNETA1570 does not perform fast back-to-back transactions; therefore, this bit is hardwired

to a 0.

10 − 15

Reserved

Always return 0

All 0s

TNETA1570 数据表(PDF) 52 Page - Texas Instruments

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