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TNETA1570 数据表(PDF) 7 Page - Texas Instruments

部件名 TNETA1570
功能描述  ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE
PDF  68 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETA1570 数据表(HTML) 7 Page - Texas Instruments

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TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64BIT PCIHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
control-memory interface
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
CMAD17 −
CMAD0
61,
59 − 57,
55 − 50,
48,
46 − 41,
39
O
(CMOS)
Control-memory address. CMAD17− CMAD0 contains an 18-bit physical address to the control
memory.
CMDATA31 −
CMDATA0
35 − 33,
31 − 29,
27 − 25,
23 − 18,
16,
14 − 9,
7,
5− 1,
240,
238 − 236
I
(TTL)
O
(CMOS)
Control-memory data. CMDATA31 − CMDATA0 contains 32-bit data to/from the control memory.
CMOE
36
O
(CMOS)
Control-memory output enable. When CMOE is active low, the address is valid and data is read
into the TNETA1570 on the rising edge of CMOE.
CMWE
37
O
(CMOS)
Control-memory write enable. When CMWE is active low, the address and data are valid.
boundary-scan interface
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
TCK
103
I
(TTL)
Test clock. TCK clocks the test-access-port (TAP) operation.
TDI
106
I
(TTL)
Test data input. TDI shifts serial-test data and instructions into the device during (TAP) operation.
TDO
105
O
(TTL)
Test data output. TDO shifts serial-test data and instructions out of the device during TAP
operation.
TMS
104
I
(TTL)
Test-mode select. TMS controls the state of the TAP controller.
TRST
102
I
(TTL)
Test reset. TRST asynchronously forces the TAP controller to a known state.
test signal
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
TESTMODE
101
I
(TTL)
Test mode. TESTMODE is used for device testing. Grounded for normal operation.



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