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TNETA1570 数据表(PDF) 16 Page - Texas Instruments

部件名 TNETA1570
功能描述  ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE
PDF  68 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETA1570 数据表(HTML) 16 Page - Texas Instruments

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TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64BIT PCIHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
timing requirements (see Figure 7)
NO.
MIN
MAX
UNIT
1
tsu(PIDSEL)
Setup time, PIDSEL high before PCLK
↑
7
ns
2
tsu(PAD)
Setup time, PAD31 − PAD0 valid before PCLK
↑
7
ns
3
tsu(PCBE)
Setup time, PCBE3 − PCBE0 valid before PCLK
↑
7
ns
4
tsu(PIRDY)
Setup time, PIRDY low before PCLK
↑
7
ns
5
th(PIDSEL)
Hold time, PIDSEL high after PCLK
↑
1
ns
6
th(PAD)
Hold time, PAD31 − PAD0 valid after PCLK
↑
2
ns
7
th(PCBE)
Hold time, PCBE3 − PCBE0 valid after PCLK
↑
1
ns
8
th(PIRDY)
Hold time, PIRDY low after PCLK
↑
1
ns
operating characteristics (see Figure 7)
NO.
MIN
MAX
UNIT
9
td(PAD)
Delay time, PCLK
↑ to PAD31−PAD0 valid
2
11
ns
10
td(PTRDY)
Delay time, PCLK
↑ to PTRDY↓
2
11
ns
11
td(PDEVSEL)
Delay time, PCLK
↑ to PDEVSEL↓
2
11
ns
PCLK
(input)
PIDSEL
(input)
PAD31−
PAD0
(I/O)
PFRAME
(input)
PCBE3−
PCBE0
(input)
PIRDY
(input)
PTRDY
(output)
PDEVSEL
(output)
Address
Bus Cmd
5
1
7
BE
3
Data
8
Address
Phase
6
2
4
10
Data Phase
9
11
Figure 7. TNETA1570 Read Operation (PCI SAR as Slave)



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