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TNETA1570 数据表(PDF) 12 Page - Texas Instruments

部件名 TNETA1570
功能描述  ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE
PDF  68 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETA1570 数据表(HTML) 12 Page - Texas Instruments

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TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64BIT PCIHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
timing requirements (see Note 6 and Figure 3)
NO.
MIN
MAX
UNIT
1
tw(RESCLKH)
Pulse duration, RESCLK high
10
ns
2
tw(RESCLKL)
Pulse duration, RESCLK low
10
ns
3
tsu(RESEN)
Setup time, RESEN high before RESCLK
↑
10
ns
4
tsu(RESSOC)
Setup time, RESSOC high before RESCLK
↑
10
ns
5
tsu(RESDATA)
Setup time, RESDATA7 − RESDATA0 valid before RESCLK
↑
10
ns
6
tsu(RESPAR)
Setup time, RESPAR valid before RESCLK
↑
10
ns
7
th(RESEN)
Hold time, RESEN high after RESCLK
↑
1
ns
8
th(RESSOC)
Hold time, RESSOC high after RESCLK
↑
1
ns
9
th(RESDATA)
Hold time, RESDATA7 − RESDATA0 valid after RESCLK
↑
1
ns
10
th(RESPAR)
Hold time, RESPAR valid after RESCLK
↑
1
ns
NOTE 6: All output signals are generated on the rising edge of RESCLK. All input signals are sampled on the rising edge of RESCLK.
operating characteristics (see Note 6 and Figure 3)
NO.
MIN
MAX
UNIT
11
td(RESCLAV)
Delay time, RESCLK
↑ to RESCLAV↓
1
20
ns
12
td(RESPERR)1
Delay time, RESCLK
↑ to RESPERR↓
1
20
ns
13
td(RESPERR)2
Delay time, RESCLK
↑ to RESPERR↑
1
20
ns
NOTE 6: All output signals are generated on the rising edge of RESCLK. All input signals are sampled on the rising edge of RESCLK.
RESDATA7−
RESDATA0
(input)
RESEN
(input)
RESCLK
(input)
1
2
RESSOC
(input)
7
3
RESCLAV
(output)
Byte 1
Byte 2
Byte 3
Byte 49
Input
Ignored
Byte 50
Byte 48
Byte 51
11
If necessary
4
8
5
9
RESPAR
(input)
12
6
10
13
No Parity Error
RESPERR
(output)
Parity
Error
Figure 3. Reassembly-Cell Interface (PHY/ATM High)



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