TNETA1570 datasheet(66/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

ATM-cells-received counter

This 32-bit counter counts the number of ATM cells received and not dropped. This rollover counter causes a

bit in the status register to be set on rollover. This counter is read only and is cleared when a hardware or

software reset occurs. This counter does not clear on a read by the host.

ATM-cells-transmitted counter

This 32-bit counter counts the number of ATM cells actually transmitted. This rollover counter causes a bit in

the status register to be set on rollover. This counter is read only and is cleared when a hardware or software

reset occurs. This counter does not clear on a read by the host.

control-memory maps

normal control-memory map

Control memory is broken into three sections: pointer block, transmit section and receive section. The pointer

block contains the pointers to the receive free-buffer rings and the transmit and receive completion rings. The

transmit section contains the scheduler table and the transmit DMA state table. The receive section contains

the receive VPI/VCI DMA pointer table and the receive DMA state table. The mapping of these blocks into

control memory is shown in the following table.

MEMORY BLOCK

SIZE

(in 32-bit words)

CONTROL-MEMORY

ADDRESS (hex)

PCl OFFSET

ADDRESS (hex)

Scheduler Table

3100

00000 − 00C1B

00000 − 0306C

Reserved

228

00C1C − 00CFF

03070 − 033FC

Reserved

256

00D00 − 00DFF

03400 − 037FC

Free-Buffer Pointers

512

00E00 − 00FFF

03800 − 03FFC

RX VPI/VCI DMA

Pointer Table

4,096

01000 − 0IFFF

04000 − 07FFC

Reserved

02000 − 02007

08000 − 0801C

TX DMA State Table

8,184

02008 − 03FFF

08020 − 0FFFC

RX DMA State Table

245,760

04000 − 3FFFF

10000 − FFFFC

The memory mapping is designed to make it possible for users to design the application boards to support the

number of TX DMA states and RX DMA states used with a minimum number of SRAMs. This is achieved by

choosing the start address of the TX DMA state table and the RX DMA state table on even boundaries.

small SRAM control-memory map

If the SMALL_MAP bit is set in the configuration register (if a maximum of 512 TX DMA states and 512 RX DMA

states are to be used), address line CM AD (14) is ORed in the TNETA1570 with address line CM AD (13) and

CM AD (12). The SRAM needed is 16K

× 32.The hardware interprets address 04000−04FFF as address

03000 −03FFF creating the following control-memory map:

TNETA1570 数据表(PDF) 66 Page - Texas Instruments

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