TNETA1570 datasheet(50/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

host-interface overview (continued)

As a master, the TNETA1570 incorporates the following features:

D Utilizes the memory-read and memory-write PCI-bus commands

D Initiates transactions as a 32-bit or 64-bit agent (for data only)

D Initiates transactions as a 32-bit agent (for control structures)

D Performs multiple data-cycle transfers when possible up to a maximum of 12 data cycles

D Allows the user to specify the maximum number of times a transaction is retried before flagging a

system-error condition

signal descriptions

The following is a summary of the PCI-bus signals with a brief description of each signal. An overbar is used

to denote an active-low signal. The pin names are found by adding the prefix PCI_ to the signal names. The

definitions of the electrical types used in the signal descriptions are as follows:

TYPE

DESCRIPTION

Standard

input

Input is a standard input-only signal.

Standard

output

Output is a standard totem-pole active driver.

3 state

Three-state is a bidirectional input/output signal.

Sustained

3 state

Sustained 3-state is an active-low 3-state signal owned and driven

by only one agent at a given time.

Open drain

Open drain allows multiple devices to share signals as a wired-OR.

In addition to the standard PCI-interface signals, two additional sideband signals are also defined. These signals

are SB(bit 0) and SB(bit 1). They give the size of the transfer when the TNETA1570 is the bus master. These

signals are defined as follows:

SB (bit 1)

SB (bit 0)

DESCRIPTION

4-byte transfer

16-byte transfer except for receive completion ring

Payload transfer

Transfer to receive completion ring 20-byte transfers

Sideband signals are synchronous to the address phase of bus-mastering operations by the TNETA1570.

Sideband signals are not changed upon a bus retry after disconnect. The sideband signals are always active

(i.e., they are always driven by the TNETA1570). They comply with point-to-point PCI-bus timing.

configuration space definition

As described in the PCI-local bus specification revision 2.0, the TNETA1570 provides a 64-byte configuration

space that can be accessed by system software for configuration, initialization, and error handling. The

TNETA1570 responds to type 0 configuration accesses. The following map describes the 64-byte configuration

space.

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