TNETA1570 datasheet(41/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

receive free-buffer FIFO (continued)

The FIFO/free-buffer ring entry consists of one 32-bit word as shown below:

ENTRY

DESCRIPTION

Word 0

Control, free-buffer pointer

The definitions of the fields contained in each word entry are given below:

word 0

Control (bits 31 − 30)

Start-of-Next-Data-Buffer Pointer (bits 29 − 0)

OWN (bit 31)

This bit is set by the host to indicate that the buffer is available for use by the TNETA1570. The TNETA1570

uses the free-ring entry if the OWN bit is set. If the OWN bit is not set, buffer starvation occurs. The TNETA1570

clears the OWN bit after acquiring the buffer, releasing the ring location to the host. For the FIFO-based

mechanism, the TNETA1570 does not write back to the entry. The FIFO implementation must ensure that OWN

is set properly to indicate whether the entry in the free-buffer FIFO is valid or not.

reserved (bit 30)

start-of-next-data-buffer pointer (bits 29 −0)

This field contains the address of an available buffer, aligned on either a 32- or 64-bit boundary, depending upon

whether a 32- or 64-bit PCI interface is selected. Only the upper 30 bits of the address are written to this entry.

The lower two address bits are always zero.

receive data buffers

Addressing

New buffer using free-buffer rings. The address is stored in the RX free-buffer ring.

New buffer using free-buffer FIFO. The address is stored in the RX free-buffer FIFO.

Ongoing buffer: Address stored in RX DMA state table

Size

Min size: buffer descriptor + 48-byte payload data

Max size: buffer descriptor + 3145728-byte payload data

Buffers/packets

(buffer chains) supported

Max number of packets simultaneously being reassembled: 30720

Max number of queued free buffers on one RX free-buffer ring: 1024

Max number of queued free buffers on all RX free-buffer rings: 1024

× 256 = 262144

Max total number of queued free buffers on one RX free-buffer FIFO: limited by the FIFO size

The data-buffer-descriptor entry and the received user data are both placed in the data buffer as shown. The

data-buffer-descriptor entry consists of four 32-bit words and the user data contains (N x 48) bytes of

information, except for the last buffer in the chain; therefore, the total size of the data buffer, except for the last

buffer in the buffer chain, is (N x 48) + 16 bytes. The value of N is greater than zero. This requirement ensures

that all buffers except the last buffer in the chain contains an integral number of ATM-cell payloads. The buffer

size is user configurable from 48 byte to 3.1M byte of user data. The total receive-data buffer must be at least

64 bytes and contain at least 48 byte of data. The maximum total size is 3145726 bytes.

Data-buffer descriptor entry (four 32-bit words)

User information [(N x 48) bytes]

TNETA1570 数据表(PDF) 41 Page - Texas Instruments

TNETA1570 数据表(HTML) 41 Page - Texas Instruments

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