TNETA1570 datasheet(61/68 Pages) TI1

61 / 68 page

TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

PCI_

STATUS

RESERVED

PCI_MODE

RX_

FRZ

TX_FRZ

CP_RX

RX_IRR

HEC_R

UP_R

APD_R

ACR_R

ACT_R

CP_TX

bits

31 − 16

bits

15 − 11

bit 10

bit 9

bit 8

bit 7

bit 6

bit 5

bits 4

bit 3

bit 2

bit 1

bit 0

PCI_STATUS (bits 31 −16)

These sixteen bits of the status register contain the PCI-interface status bits. They are located here to allow for

a single 32-bit word access to acquire the complete status of the TNETA1570.

PCI_MODE (bit 10)

This bit is used to indicate either 32-bit or 64-bit PCI interface. When this bit is high, the 64-bit PCI operation

is selected at reset.

RX_FRZ (receive freeze) (bit 9)

The TNETA1570 sets the RX_FRZ bit when a receive-completion-ring overflow is detected. It is cleared on read.

TX_FRZ (transmit freeze) (bit 8)

The TNETA1570 sets the TX_FRZ bit when a transmit-completion-ring overflow is detected. It is cleared on

read.

CP_RX (receive completion ring) (bit 7)

This bit is set when the reassembly of a packet is completed and the receive completion ring with interrupt is

updated.

RX_IRR (receive unknown register set) (bit 6)

This bit of the status register is set when a value is written to the RX-unknown register.

HEC_R (bit 5)

This bit is set when the HEC-error counter rolls over.

UP_R (unknown protocols rollover) (bit 4)

This bit is set when the unknown-protocols counter rolls over.

APD_R (AAL5 CPCS PDU discard counter rollover) (bit 3)

This bit is set when the AAL5 CPCS PDU discard counter rolls over.

ACR_R (ATM cells received counter rollover) (bit 2)

This bit is set when the ATM-cells-received counter rolls over.

ACT_R (ATM cells transmitted counter rollover) (bit 1)

This bit is set when the ATM-cells-transmitted counter rolls over.

CP_TX (transmit completion ring) (bit 0)

This bit is set when the segmentation of a buffer or packet is completed and the transmit-completion ring with

interrupt is updated.

TNETA1570 数据表(PDF) 61 Page - Texas Instruments

TNETA1570 数据表(HTML) 61 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载