TNETA1570 datasheet(42/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

receive data buffers (continued)

The descriptor entry contains four 32-bit words:

ENTRY

DESCRIPTION

Word 0

Reserved

Word 1

Control field, start-of-next-buffer pointer

Word 2

4-byte ATM header

Word 3

User defined

The definitions of the fields inside each word are:

word 0

Reserved (bits 31 − 0)

This word is not used by the TNETA1570 and reserved for future revisions of the TNETA1570.

word 1

Control (bits 31−30)

Start of Next RX Data-Buffer Pointer (bits 29−0)

start of packet (bit 31)

This bit is set by the TNETA1570 to indicate that this is the first buffer in the received packet.

end of packet (bit 30)

This bit is set by the TNETA1570 to indicate that this is the last buffer in the received packet.

start of next RX data-buffer pointer (bits 29 −0)

This word provides the location of the next data-buffer in the data-buffer chain. If this is the last data-buffer in

the chain, this word is zero (0). This pointer is set by the TNETA1570.

word 2

ATM Header Byte 1

ATM Header Byte 2

ATM Header Byte 3

ATM Header Byte 4

This word contains the first four header bytes from the ATM packet undergoing reassembly.

word 3

User Defined (bits 31 − 0)

user defined (bits 31 −0)

This field is not overwritten by the TNETA1570 and is available for use by the user.

receive completion rings

Addressing

In host memory. The entries are addressed using the RX completion-ring pointers.

Size: set in the RX

completion-ring-size registers

Max logical entries: 1024

Max 32-bit words: 8192

Min logical entries: 1

Min 32-bit words: 8

The TNETA1570 provides support for two RX completion rings that reside in host memory: the receive completion

ring with interrupt and the receive completion ring without interrupt. The difference between the rings is that when

an entry is posted to the receive completion ring with interrupt an interrupt is generated, and when an entry is

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