TNETA1570 datasheet(60/68 Pages) TI1

60 / 68 page

TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

SMALL_MAP (bit 6)

If the SMALL_MAP bit is set in the configuration register, address line CM_AD(14) is ORed in the TNETA1570

with address line CM_AD (13) and CM_AD (12) The SRAM needed is 16K x 32. If this option is chosen, a

maximum of 512 TX DMA states and 512 RX DMA states are used. Alternative control-memory map is used

to support small SRAM configuration.

EN_TX (bit 5)

The EN_TX bit allows the host to disable packet segmentation and any payload-data transfer from the host to

the link. It is set high to enable normal transmit processing and set to zero to disable such processing. It is set

to zero on reset, disabling transmit operation until various configuration registers, the scheduler table, and the

DMA blocks are configured by the host. The transfer of the new cells from PCI bus to TNETA1570 is inhibited

when the EN_TX bit is disabled; however, cells already in the output buffer are forwarded to the PHY layer. This

bit is set to zero by the TNETA1570 upon TX_FRZ condition and set high by the host allowing resumption of

normal operation.

EN_RX (bit 4)

The EN_RX bit allows the host to disable packet reassembly. All cells from the PHY layer are dropped when

the EN_RX bit is zero. The EN RX bit is set high to enable normal processing. It is set to zero on reset, disabling

receive operation until various configuration registers and the DMA blocks are reconfigured by the host. The

transfer of new cells from the ATM link to the receive buffer is inhibited when the EN_RX bit is disabled. This

bit is set to zero by the TNETA1570 upon RX_FRZ condition and set high by the host allowing resumption of

normal operation.

ENDN_EL (bits 3, 2)

The endian-select bits allows the host to configure the endian mode for TNETA1570 as shown below. The

TNETA1570 is configured for little-endian mode immediately after reset.

00 = little endian

01 = big endian

1X = reserved

BP_SEL (bit 1)

If interrupt is enabled, this bit selects the criteria used for the transmit-completion ring. When the

buffer-/packet-interrupt-select bit is set to high, an interrupt is generated by the TNETA1570 upon posting to the

transmit-completion ring on a per-packet basis. An interrupt is generated on a per-buffer basis when the bit is

set to low.

EN_RAT (bit 0)

When this bit is set high (=1), the reassembly-aging timer is enabled. The global-timer register and the maximum

RX DMA-state table-size register must be initialized for timer operation. When EN_RAT is set low

(= 0), no reassembly aging on any receive DMA channel occurs.

status register

This register contains information on the current operating state of the device. When an interrupt occurs, the

host can read this register to determine the cause of the interrupt. The lower ten bits (9 −0) are configured as

clear-on-read, (i.e., the contents of the lower ten bits of this register are cleared when the register is read). The

higher 22 bits (bits 31−0) remain unchanged on read. This register is read only and is accessed as a 32-bit word,

although not all 32 bits may be used. This register is cleared upon a hardware or software reset.

TNETA1570 数据表(PDF) 60 Page - Texas Instruments

TNETA1570 数据表(HTML) 60 Page - Texas Instruments

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