TNETA1570 datasheet(20/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

segmentation overview

The segmentation operation of the TNETA1570 can operate on three types of packets: AAL5 packets,

transparent (undefined)-AAL packets with end-of-packet (EOP) termination in the PTI field of the ATM header,

and transparent AAL-packets without special ATM-header processing for the last cell of the packet. Up to 1023

separate virtual circuits (VCs) can be segmented concurrently, and each corresponds to its own host DMA

channel maintained by the TNETA1570. Any VC (DMA channel) can be configured to segment any one of the

three packet types. Each packet type is stored in host memory in either single buffers or buffer chains. The

buffer-chaining mechanism allows segmentation to begin on a packet before all of the packet contents are

established in buffers.

For each VC, the host establishes a VPI/VCI connection and assigns it to a transmit packet-segmentation ring

that is assigned a free-segmentation DMA channel controlled by the TNETA1570. Memory structures initialized

by the host for packet segmentation on a virtual channel include the scheduler table (control memory), the

transmit completion-ring pointers (register), and word 3 of the DMA state entry for the DMA channel assigned

to the VC (control memory). The ON bit (bit 31) of word 3 in the DMA state entry activates the DMA channel

for packet segmentation. The lower 30 bits of word 3 form the packet-segmentation-ring pointer. The

TNETA1570 registers that need to be initiated by the host for segmentation are the configuration register,

interrupt-mask register, TX completion ring with and without interrupt registers, and TX packet-segmentation

ring-size register.

When at least one buffer of a packet in an established DMA channel is prepared for processing, the RDY bit

in the buffer header is set to a 1 indicating that the TNETA1570 has control of the buffer and the start-of-packet

(SOP) bit is set in the header. The address of the next buffer, if used, must be known at this time and placed

in the appropriate buffer-descriptor location. After this, a pointer to the first buffer of the packet is placed in the

next entry of the DMA packet-segmentation ring, and the OWN bit of the entry is set to 1 indicating to the

TNETA1570 that a packet is ready for processing. The host indicates the readiness of each subsequent buffer

to the TNETA1570 upon completion of its contents preparation. The last buffer of a packet must have the EOP

bit set in the buffer descriptor.

Upon a buffer-segmentation completion, the TNETA1570 posts an entry in the next position of a transmit-

completion ring. The completion ring with and without interrupt selection is initialized by the host in the buffer

descriptor. If a completion ring with interrupt entry is posted and the TNETA1570 interrupt-mask register permits,

an interrupt is generated on the PCI bus and an interrupt indication is generated in the status register.

The memory structure for scheduling transmit-DMA-channel service is the scheduler table located in the control

memory. The TNETA1570 continuously reads through each entry in the scheduler table from the top down. Two

transmit-DMA-channel pointers are located in each 32-bit word entry in this table.

Each entry of the scheduler table is an opportunity for packet segmentation. Each entry indexes the

transmit-DMA channel used to extract a single cell during packet segmentation. If the DMA channel is on, the

segmentation procedure can continue. If the scheduler-table entry contains zero or the DMA channel is off, no

packet segmentation is performed and the next scheduler-table entry is examined.

After determining that a transmit-DMA channel is on, packet segmentation for the channel is initiated. If the ACT

bit in the TX DMA state table is set, a packet is begun and not ended. Also, if the current data-byte-count field

for the entry is greater than zero, a buffer is in use and packet segmentation resumes from the DMA current

buffer-address field. A current data-byte-count field of zero causes the TNETA1570 to use the next

buffer-address field to acquire a new buffer from host memory before packet segmentation can begin.

When acquiring a new buffer, the RDY bit of the buffer is examined. If the RDY bit is set, the buffer descriptor

is loaded into the DMA-state entry. Packet segmentation for the DMA channel is terminated for the cell

opportunity if the buffer RDY bit is not set in the buffer.

TNETA1570 数据表(PDF) 20 Page - Texas Instruments

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