AM79C971VCW datasheet(180/265 Pages) AMD

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Am79C971

P R E L I M INARY

BCR34: MII Management Data Register

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

MIIMD

MII Management Data. MIIMD is

the data port for operations on the

MII management interface (MDIO

and MDC). The Am79C971 de-

vice builds management frames

using the PHYAD and REGAD

values from BCR33. The opera-

tion code used in each frame is

based upon whether a read or

write operation has been per-

formed to BCR34. Read cycles

on the MII management interface

are invoked when BCR34 is read.

Upon completion of the read cy-

cle, the 16-bit result of the read

operation is stored in MIIMD.

Write cycles on the MII manage-

ment interface are invoked when

BCR34 is written. The value writ-

ten to MIIMD is the value used in

the data field of the management

write frame.

When the PHYAD (BCR33, bits

9-5) is 11111b the data written

and read from the MIIMD will be

from the internal PHY only. No

MII management frame will be

sent across the MII when the

PHYAD is 11111b.

Read/Write accessible always.

MIIMD

undefined

after

H_RESET and is unaffected by

S_RESET and the STOP bit.

BCR35: PCI Vendor ID Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

VID

Vendor ID. The PCI Vendor ID

identifies the manufacturer of the

Am79C971

controller.

AMD’s

Vendor ID is 1022h. Note that this

Vendor ID is not the same as the

Manufacturer ID in CSR88 and

CSR89. The Vendor ID is as-

signed by the PCI Special Inter-

est Group.

The Vendor ID is not normally

programmable,

but

the

Am79C971 controller allows this

due to legacy operating systems

that do not look at the PCI Sub-

system Vendor ID and the Ven-

dor ID to uniquely identify the

add-in board or subsystem that

the Am79C971 controller is used

in.

Note: If the operating system

or the network operating sys-

tem supports PCI Subsystem

Vendor ID and Subsystem ID,

use those to identify the add-in

board or subsystem and pro-

gram the VID with the default

value of 1022h.

VID is aliased to the PCI configu-

ration space register Vendor ID

(offset 00h).

Read accessible always. VID is

read only. Write operations are

ignored. VID is set to 1022h by

H_RESET and is not affected by

S_RESET or by setting the STOP

bit.

Initialization Block

When SSIZE32 (BCR20, bit 8) is set to 0, the software

structures are defined to be 16 bits wide. The base ad-

dress of the initialization block must be aligned to a

DWord boundary, i.e., CSR1, bit 1 and 0 must be

cleared to 0. When SSIZE32 is set to 0, the initialization

block looks like Table 42.

Note: The Am79C971 controller performs DWord ac-

cesses to read the initialization block. This statement is

always true, regardless of the setting of the SSIZE32

bit.

When SSIZE32 (BCR20, bit 8) is set to 1, the software

structures are defined to be 32 bits wide. The base ad-

dress of the initialization block must be aligned to a

DWord boundary, i.e., CSR1, bits 1 and 0 must be

cleared to 0. When SSIZE32 is set to 1, the initialization

block looks like Table 43

AM79C971VCW 数据表(PDF) 180 Page - Advanced Micro Devices

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