AM79C971VCW datasheet(179/265 Pages) AMD

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Am79C971

179

P R E L I M INARY

bit will allow the Am79C971 con-

troller to work seamlessly with the

Micro Linear 6692 PHY. See the

section on Working with Micro

Linear 6692 for details.

Read/Write accessible always.

MII

µL is set to 0 by H_RESET

and is unaffected by S_RESET

and the STOP bit.

MII

µL is only

valid when the internal Network

Port Manager is scanning for a

network port.

MIIILP

Media Independent Interface In-

ternal Loopback. When set, this

bit will cause the internal portion

of the MII data port to loopback

on itself. The interface is mapped

the

following

way.

The

TXD[3:0] nibble data path is

looped back onto the RXD[3:0]

nibble data path. TX_CLK is

looped back as RX_CLK. TX_EN

is looped back as RX_DV. CRS is

correctly OR’d with TX_EN and

RX_DV and always encompass-

es the transmit frame. TX_ER is

looped back as RX_ER. Howev-

er, TX_ER will not get asserted

by the Am79C971 controller to

signal an error. The TX_ER func-

tion is reserved for future use.

Read/Write accessible always.

MIIILP is set to 0 by H_RESET

and is unaffected by S_RESET

and the STOP bit.

FCON

Fast Configuration Mode. When

set this bit will force the internal

Management Port State Machine

into a Fast Configuration Mode.

During this mode, the Manage-

ment Port State Machine will not

attempt to start Auto-Negotiation

on the internal as well as the ex-

ternal PHY. Instead, it will rely on

link beats for link pass state. This

will accelerate the automatic port

selection on the Am79C971 con-

troller.

Read/Write accessible always.

FCON is set to 0 by H_RESET

and is unaffected by S_RESET

and the STOP bit. FCON is only

valid when the internal Network

Port Manager is scanning for a

network port. See Table 40.

BCR33: MII Address Register

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-10 RES

Reserved locations. Written as

zeros and read as undefined.

9-5

PHYAD

MII Management Frame PHY Ad-

dress. PHYAD contains the 5-bit

PHY Address field that is used in

the management frame that gets

clocked out via the MII manage-

ment port pins (MDC and MDIO)

whenever a read or write transac-

tion occurs to BCR34. The inter-

nal

PHY

device

always

addressed as 11111b. The MII

management frame will not ap-

pear on the MII when reading or

writing to the internal PHY. This is

done for MII compatibility sake.

The Network Port Manager cop-

ies

the

PHYAD

after

the

Am79C971 controller reads the

EEPROM and uses it to commu-

nicate with the external PHY. The

PHY

address

must

pro-

grammed into the EEPROM prior

to starting the Am79C971 con-

troller.

Read/Write accessible always.

PHYAD

undefined

after

H_RESET and is unaffected by

S_RESET and the STOP bit.

4-0

REGAD

MII Management Frame Register

Address. REGAD contains the 5-

bit Register Address field that is

used in the management frame

that gets clocked out via the MII

management port pins (MDC and

MDIO) whenever a read or write

transaction occurs to BCR34.

Read/Write accessible always.

REGAD

undefined

after

H_RESET and is unaffected by

S_RESET and the STOP bit.

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