AM79C971VCW datasheet(178/265 Pages) AMD

178 / 265 page

178

Am79C971

P R E L I M INARY

Read/Write accessible always.

APEP

set

during

H_RESET and is unaffected by

S_RESET and the STOP bit.

10-8

APDW

MII Auto-Poll Dwell Time. APDW

determines the dwell time be-

tween MII Management Frames

accesses

when

Auto-Poll is

turned on. See Table 41.

Read/Write accessible always.

APDW is set to

100h after

H_RESET and is unaffected by

S_RESET and the STOP bit.

DANAS

Disable

Auto-Negotiation

Auto

Setup. When DANAS is set, the

Am79C971

controller

after

H_RESET or S_RESET will re-

main dormant and not automati-

cally startup the Auto-Negotiation

section or the enhanced automat-

ic port selection section. Instead,

the Am79C971 controller will wait

for the software driver to setup

the Auto-Negotiation portions of

the device. The automatic port

selection for Am79C971 control-

ler will resemble the Pcnet-PCI II

controller. The MII programming

in BCR33 and BCR34 is still valid.

The Am79C971 controller will not

generate

any

management

frames unless Auto-Poll is en-

abled.

Read/write

accessible

always.

DANAS is set to 0 by H_RESET

and is unaffected by S_RESET

and the STOP bit.

XPHYRST

External PHY Reset. When XPH-

YRST is set, the Am79C971 con-

troller after an H_RESET or

S_RESET will issue an MII man-

agement frames that will reset the

external PHY. This bit is needed

when there is no way to guaran-

tee the state of the external PHY.

This bit must be reprogrammed

after every H_RESET.

Read/Write accessible always.

XPHYRST

set

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYRST is only valid when the

internal Network Port Manager is

scanning for a network port.

XPHYANE

External PHY Auto-Negotiation

Enable. This bit will force the ex-

ternal PHY into enabling Auto-

Negotiation. When set to 0 the

Am79C971 controller will send a

MII management frame disabling

Auto-Negotiation.

Read/Write accessible always.

XPHYANE

set

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYANE is only valid when the

internal Network Port Manager is

scanning for a network port.

XPHYFD

External PHY Full Duplex. When

set, this bit will force the external

PHY into full duplex when Auto-

Negotiation is not enabled.

Read/Write accessible always.

XPHYFD

set

H_RESET, and is unaffected by

S_RESET and the STOP bit.

XPHYFD is only valid when the

internal Network Port Manager is

scanning for a network port.

XPHYSP

External PHY Speed. When set,

this bit will force the external PHY

into 100 Mbps mode when Auto-

Negotiation is not enabled.

Read/Write accessible always.

XPHYSP

set

H_RESET, and is unaffected by

S_RESET and the STOP bit.

XPHYSP is only valid when the

internal Network Port Manager is

scanning for a network port.

2MII

µL

Media Independent Interface for

Micro Linear 6692. When set, this

Table 41.

APDW Values

APDW

Auto-Poll

 Dwell Time

000

Continuous (26

µs @ 2.5 MHz)

001

Every 128 MDC cycles (103

µs @ 2.5 MHz)

010

Every 256 MDC cycles (206

µs @ 2.5 MHz)

011

Every 512 MDC cycles (410

µs @ 2.5 MHz)

100

Every 1024 MDC cycles (819

µs @ 2.5 MHz)

101

Every 2048 MDC cycles (1640

µs @ 2.5 MHz)

110-111

Reserved

AM79C971VCW 数据表(PDF) 178 Page - Advanced Micro Devices

AM79C971VCW 数据表(HTML) 178 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AM79C971VCW 数据表(PDF) 178 Page - Advanced Micro Devices

AM79C971VCW 数据表(HTML) 178 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载