AM79C971VCW datasheet(176/265 Pages) AMD

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176

Am79C971

P R E L I M INARY

cess to EBDATA (BCR30). When

EBADDRL reaches FFFFh and

LAAINC is set to 1, the Expansion

Port Lower Address (EPADDRL)

will roll over to 0000h. When the

LAAINC bit is set to 0, the Expan-

sion Port Lower Address will not

be affected in any way after an

access to EBDATA (BCR30) and

must be programmed.

Read accessible always; write

accessible only when the STOP

bit is set. LAINC is 0 after

H_RESET and is unaffected by

S_RESET or the STOP bit.

13-4

RES

Reserved locations. Written as

zeros and read as undefined.

3-0

EPADDRU

Expansion Port Address Upper.

This upper portion of the Expan-

sion Bus address is used to pro-

vide addresses for Flash/EPROM

port accesses.

Read accessible always; write

accessible only when the STOP

bit is set or when SRAM SIZE

(BCR25, bits 7-0) is 0. EPADD-

RU is undefined after H_RESET

and is unaffected by S_RESET or

the STOP bit.

BCR30: Expansion Bus Data Port Register

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

EBDATA

Expansion Bus Data Port. EBDA-

TA is the data port for operations

on the Expansion Port accesses

involving SRAM and Flash ac-

cesses. The type of access is set

by the FLASH bit (BCR 29, bit

15). When the FLASH bit is set to

1, the Expansion Bus access will

follow the Flash access timing.

When the FLASH bit is set to 0,

the Expansion Bus access will

follow the SRAM access timing.

Note: It is important to set the

FLASH bit and load Expansion

Port Address EPADDR (BCR28,

BCR29) with the required ad-

dress before attempting read or

write to the Expansion Bus data

port. The Flash and SRAM ac-

cesses use different address

phases. Incorrect configuration

will result in a possible corruption

of data.

Flash read cycles are performed

when BCR30 is read and the

FLASH bit (BCR29, bit 15) is set

to 1. Upon completion of the read

cycle, the 8-bit result for Flash ac-

cess is stored in EBDATA[7:0],

EBDATA[15:8]

undefined.

Flash write cycles are performed

when BCR30 is written and the

FLASH bit (BCR29, bit 15) is set

to 1. EBDATA[7:0] only is valid

for write cycles.

SRAM read cycles are performed

when BCR30 is read and the

FLASH bit (BCR29, bit 15) is set

to 0. Upon completion of the read

cycle, the 16-bit result for SRAM

access is stored in EBDATA.

Write cycles to the SRAM are in-

voked when BCR30 is written

and the FLASH bit (BCR29, bit

15) is set to 0. Byte writes to the

SRAM must use a read-modify-

write scheme since the word is al-

ways valid for SRAM write or

read accesses.

Read and write accessible only

when the STOP is set or when

SRAM SIZE (BCR25, bits 7-0) is

0. EBDATA is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

BCR31: Software Timer Register

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

STVAL

Software Timer Value. STVAL

controls the maximum time for

the Software Timer to count be-

fore

generating

the

STINT

(CSR7, bit 11) interrupt. The Soft-

ware Timer is a free-running timer

that is started upon the first write

to STVAL. After the first write, the

Software Timer will continually

count and set the STINT interrupt

at the STVAL period.

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