AM79C971VCW datasheet(173/265 Pages) AMD

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Am79C971

173

P R E L I M INARY

7-0

SRAM_SIZE SRAM Size. Specifies the upper

8 bits of the 16-bit total size of the

SRAM

buffer.

Each

bit

SRAM_SIZE accounts for a 512-

byte page. The starting address

for the lower 8 bits is assumed to

be 00h and the ending address

for the lower is assumed to be

FFh. Therefore, the maximum ad-

dress range is the starting ad-

dress of 0000h to ending address

((SRAM_SIZE

+1)

256

words)

FFFFh.

SRAM_SIZE value of all zeros

specifies that no SRAM is present

and the internal FIFOs will be

joined into a contiguous FIFO

similar to the PCnet-PCI II con-

troller.

Note:

The

minimum

allowed

number of pages is eight for nor-

mal

network

operation.

The

Am79C971 controller will not op-

erate correctly with less than the

eight pages of memory. When

the minimum number of pages is

used, these pages must be allo-

cated four each for transmit and

receive. Also note that a “No

SRAM configuration” is only valid

for 10Mb mode. In 100Mb mode,

SRAM is mandatory and must al-

ways be used.

CAUTION:

Programming

SRAM_BND and SRAM_SIZE

to the same value will cause

data corruption except in the

case where SRAM_SIZE is 0.

Read accessible always; write

accessible only when the STOP

bit is set. SRAM_SIZE is set to

000000b during H_RESET and is

unaffected

S_RESET

STOP.

BCR26: SRAM Boundary Register

Bit

Name

Description

Note: Bits 7-0 in this register are programmable

through the EEPROM.

31-8

RES

Reserved locations. Written as

zeros and read as undefined.

7-0

SRAM_BND

SRAM Boundary. Specifies the

upper 8 bits of the 16-bit address

boundary where the receive buffer

begins in the SRAM. The transmit

buffer in the SRAM begins at ad-

dress 0 and ends at the address

located just before the address

specified by SRAM_BND. There-

fore, the receive buffer always be-

gins on a 512 byte boundary. The

lower bits are assumed to be ze-

ros. SRAM_BND has no effect in

the Low Latency Receive mode.

Note:

The

minimum

allowed

number of pages is four. The

Am79C971 controller will not op-

erate correctly with less than four

pages of memory per queue. See

Table 37 for SRAM_BND pro-

gramming details.

Table 37.

SRAM_BND Programming

CAUTION:

Programming

SRAM_BND and SRAM_SIZE

to the same value will cause

data corruption except in the

case where SRAM SIZE is 0.

Read accessible always; write

accessible only when the STOP

bit is set. SRAM_BND is set to

00000000b

during

H_RESET

and is unaffected by S_RESET or

STOP.

BCR27: SRAM Interface Control Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

PTR TST

Reserved. Reserved for manu-

facturing tests. Written as zero

and read as undefined.

SRAM Addresses

SRAM_BND

[7:0]

Lower Address

[7:0]

Minimum

SRAM_BND

address

04h

00-FFh

Maximum

SRAM_BND

address

FCh

00-FFh

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