AM79C971VCW datasheet(175/265 Pages) AMD

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Am79C971

175

P R E L I M INARY

CAUTION: Care should be ex-

ercised when choosing the PCI

clock pin because of the nature

of the PCI clock signal. The PCI

specification states that the

PCI clock can be stopped. If

that can occur while it is being

used for the Expansion Bus

clock data, corruption will re-

sult.

CAUtiON: The external clock

source used to drive the EB-

CLK pin must be a continuous

clock source at all times.

2-0

CLK_FAC

Clock Factor. These bits are used

to select whether the clock select-

ed by EBCS is used directly or if it

is divided down to give a slower

clock for running the Expansion

Bus access cycles. The possible

factors are given in Table 39.

Read accessible always; write

accessible only when the STOP

bit is set. CLK_FAC is set to 000b

during H_RESET and is unaffect-

ed by S_RESET or STOP.

BCR28: Expansion Bus Port Address Lower (Used

for Flash/EPROM and SRAM Accesses)

Bit

Name

Description

31-8

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

EPADDRL

Expansion Port Address Lower.

This address is used to provide

addresses for the Flash and

SRAM port accesses.

SRAM

accesses

are

started

when a read or write is performed

on BCR30 and the FLASH (BCR

29, bit 15) is set to 0. During

SRAM accesses only bits in the

EPADDRL are valid. Since all

SRAM accesses are word orient-

ed only, EPADDRL[0] is the least

significant word address bit. On

any byte write accesses to the

SRAM, the user will have to fol-

low

the

read-modify-write

scheme. On any byte read ac-

cesses to the SRAM, the user will

have to chose which byte is

needed from the complete word

returned in BCR30.

Flash accesses are started when

a read or write is performed on

BCR30 and the FLASH (BCR 29,

bit 15) is set to 1. During Flash

accesses all bits in EPADDR are

valid.

Read accessible always; write

accessible only when the STOP

is set or when SRAM SIZE

(BCR25, bits 7-0) is 0. EPADDRL

is undefined after H_RESET and

is unaffected by S_RESET or

STOP.

BCR29: Expansion Port Address Upper (Used for

Flash/EPROM Accesses)

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

FLASH

Flash Access. When the FLASH

bit is set to 1 the Expansion Bus

access will be a Flash cycle.

When FLASH is set to 0 the Ex-

pansion Bus access will be a

SRAM cycle. For a complete de-

scription see the section on Ex-

pansion Bus Interface. This bit is

only applicable to reads or writes

to EBDATA (BCR30). It does not

affect Expansion ROM accesses

from the PCI system bus.

Read accessible always; write

accessible only when the STOP

bit is set. FLASH is 0 after

H_RESET and is unaffected by

S_RESET or the STOP bit.

LAAINC

Lower Address Auto Increment.

When the LAAINC bit is set to 1,

the Expansion Port Lower Ad-

dress will automatically increment

by one after a read or write ac-

Table 39.

CLK_FAC Values

CLK_FAC

Clock Factor

000

001

1/2 (divide by 2)

010

Reserved

011

1/4 (divide by 4)

1XX

Reserved

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