TNETV2664FIBZWT datasheet(102/249 Pages) TI1

102 / 249 page

TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, PCI pins span across the following Pin Mux Blocks: Host Block,

EMIFA Block Sub-Block 0 and Sub-Block 3, PCI Data Block, and GPIO Block. For proper PCI operation, PCI must be selected in all of these Pin

Mux Blocks.

There is only one EMAC peripheral on the C6424 device, even though the pins for MII mode and the pins for RMII modes are brought out to

different locations. The EMAC MII mode pins are in the Host Block, while EMAC RMII mode pins are only in the EMIFA Block. The user is only

allowed to select either the MII pins or the RMII pins. The operation is undefined if the user attempts to select both MII pins and RMII pins.

Table 3-21 provides a different view of the Host Block pin muxing, showing the Host Block function based on PINMUX1 settings. The selection

options are also shown pictorially in Figure 3-10.

If EMAC operation is desired, EMAC must be placed in reset before programming PINMUX1.HOSTBK to select EMAC pins.

Table 3-21. Host Block Function Selection

PINMUX1 SETTING

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

PCIEN(1)

HOSTBK

PCI: PCICLK, PCBE2, PCBE1, PCBE0, PFRAME, PIDRDY, PTRDY, PDEVSEL, PSTOP, PPER,

PCI

000

PSERR, PPAR, AD[18:05], AD[03]

(Default if PCIEN = 1)

Internal pullup/pulldown on all these pins are disabled.

001 to 111

Reserved

GPIO (27)

000

GPIO: GP[83:57]

(Default if PCIEN = 0)

HPI: HHWIL, HCNTL[1:0], HR/W, HDS2, HDS1, HRDY, HCS, HINT, HAS, HD[15:0]

001

HPI + GPIO (1)

GPIO: GP[57]

VLYNQ: VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0], VLYNQ_TXD[3:0]

010

VLYNQ + GPIO (17)

GPIO: GP[83:67]

VLYNQ: VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0], VLYNQ_TXD[3:0]

EMAC (MII): TXCLK, CRS, COL, TXD[3:0], RXDV, TXEN, RXER, RXCLK, RXD[3:0]

011

VLYNQ + EMAC (MII) + MDIO

MDIO: MDC, MDIO

If EMAC operation is desired, EMAC must be placed in reset before programming

PINMUX1.HOSTBK or PINMUX0.RMII to select EMAC pins.

(1)

If PCIEN = 1, the internal pullup/pulldown on all Host Block pins are disabled. If PCIEN = 0, the internal pullup/pulldown on all Host Block pins are enabled.

102

Device Configurations

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