TNETV2664FIBZWT datasheet(105/249 Pages) TI1

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TMS320C6424

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SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Table 3-24. GPIO Block Function Selection

PINMUX1.PCIEN

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

PCI

PCI: AD0, AD1, AD2, AD4

(Default if PCIEN = 1)

GPIO (4)

GPIO: GP[3:0]

(Default if PCIEN = 0)

The PINMUX1.PCIEN field is read-only, and its setting is determined by the PCIEN configuration pin.

Based on the PCIEN configuration pin setting, the 4 pins in the GPIO Block defaults to either PCI or GPIO

function.

In addition, the VDD3P3V_PWDN.GPIO field determines the power state of the GPIO Block pins. The

GPIO Block pins default to powered up. For more details on the VDD3P3V_PWDN.GPIO field, see

Section 3.2, Power Considerations.

3.7.3.6

UART0 Data Block Muxing

This block of 2 pins consists of UART0 Data, and GPIO muxed pins. The PINMUX1.UR0DBK register field

select the pin functions in the UART0 Data Block.

Table 3-25 summarizes the 2 pins in the UART0 Data Block, the multiplexed function on each pin, and the

PINMUX configurations to select the corresponding function.

Table 3-25. UART0 Data Block Muxed Pins Selection

MULTIPLEXED FUNCTIONS

SIGNAL

UART0

GPIO

NAME

FUNCTION

SELECT

FUNCTION

SELECT

URXD0/GP[85]

URXD0

GP[85]

UR0DBK = 1

UR0DBK = 0

UTXD0/GP[86]

UTXD0

GP[86]

As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the UART0 pins span

across two Pin Mux Blocks: UART0 Data Block, and UART0 Flow Control Block. For proper UART0

operation, the two pins in the UART0 Data Block must be configured for UART0 data functions. The two

pins in the UART0 Flow Control Block are optional.

Table 3-26 provides a different view of the UART0 Data Block pin muxing, showing the UART0 Data Block

function based on PINMUX1.UR0DBK setting. The selection options are also shown pictorially in

Figure 3-10.

Table 3-26. UART0 Data Block Function Selection

PINMUX1.UR0DBK

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (2) (Default)

GPIO: GP[86:85]

UART0 Data

UART0: URXD0, UTXD0

In addition, the VDD3P3V_PWDN.UR0DAT field determines the power state of the UART0 Data Block

pins. The UART0 Data Block pins default to powered down and not operational. To use these pins, user

must first program VDD3P3V_PWDN.UR0DAT = 0 to power up the pins. For more details on the

VDD3P3V_PWDN.UR0DAT field, see Section 3.2, Power Considerations.

The UART0 Data Block features internal pullup resistors, which matches the UART inactive polarity.

3.7.3.7

UART0 Flow Control Block

This block of 2 pins consists of UART0 Flow Control, PWM0, and GPIO muxed pins. The

PINMUX1.UR0FCBK register field selects the pin functions in the UART0 Flow Control Block.

Device Configurations

105

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