TNETV2664FIBZWT datasheet(109/249 Pages) TI1

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TMS320C6424

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SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Table 3-33. Serial Port Block Muxed Pins Selection

MULTIPLEXED FUNCTIONS

SIGNAL NAME

McASP0

McBSP0/1

GPIO

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

Serial Port Sub-block 0

ACLKR0/CLKX0/GP[99]

ACLKR0

CLKX0

GP[99]

AFSR0/DR0/GP[100]

AFSR0

DR0

GP[100]

AHCLKR0/CLKR0/GP[101]

AHCLKR0

CLKR0

GP[101]

SPBK0 = 10

SPBK0 = 01

SPBK0 = 00

AXR0[3]/FSR0/GP[102]

AXR0[3]

FSR0

GP[102]

AXR0[2]/FSX0/GP[103]

AXR0[2]

FSX0

GP[103]

AXR0[1]/DX0/GP[104]

AXR0[1]

DX0

GP[104]

Serial Port Sub-block 1

AXR0[0]/FSR1/GP[105]

AXR0[0]

SPBK1 = 10/11

FSR1

SPBK1 = 01

GP[105]

ACLKX0/CLKX1/GP[106]

SPBK1 =

ACLKX0

SPBK1 = 10

CLKX1

GP[106]

01/11

AFSX0/DX1/GP[107]

SPBK1 =

AFSX0

SPBK1 = 10

DX1

GP[107]

01/11

SPBK1 = 00

AHCLKX0/CLKR1/GP[108]

AHCLKX0

SPBK1 = 10/11

CLKR1

SPBK1 = 01

GP[108]

AMUTEIN0/FSX1/GP[109]

SPBK1 =

AMUTEIN0

SPBK1 = 10

FSX1

GP[109]

01/11

AMUTE0/DR1/GP[110]

AMUTE0

SPBK1 = 10/11

DR1

SPBK1 = 01

GP[110]

As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the McBSP0 pins span

across two Pin Mux Blocks: Serial Port Sub-Block0, and Timer0 Block. For proper McBSP0 operation, the

Serial Port Sub-Block0 must be programmed to select McBSP0 function. The McBSP0 CLKS0 pin in the

Timer0 Block is optional for McBSP0 operation. CLKS0 is only needed if you desire using CLKS0 as an

external clock source to the McBSP0 internal sample rate generator.

Similarly, as discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the McBSP1

pins span across two Pin Mux Blocks: Serial Port Sub-Block1, and Timer0 Block. For proper McBSP1

operation, the Serial Port Sub-Block1 must be programmed to select McBSP1 function. The McBSP1

CLKS1 pin in the Timer0 Block is optional for McBSP1 operation. CLKS1 is only needed if you desire

using CLKS1 as an external clock source to the McBSP1 internal sample rate generator.

Table 3-34 and Table 3-35 provide a different view of the Serial Port Block. Table 3-34 shows the Serial

Port Sub-Block 0 function based on PINMUX1.SPBK0 setting. Table 3-35 shows the Serial Port Sub-Block

1 function based on PINMUX1.SPBK1 setting. These selection options are also shown pictorially in

Figure 3-10.

Table 3-34. Serial Port Sub-Block 0 Function Selection

PINMUX1.SPBK0

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (6) (default)

GPIO: GP[104:99]

McBSP0

McBSP0: CLKX0, FSX0, DX0, CLKR0, FSR0, DR0

McASP0: ACLKR0, AFSR0, AHCLKR0, AXR0[3],

McASP0 Receive, 3 Serializers

AXR0[2], AXR0[1]

Reserved

Table 3-35. Serial Port Sub-Block 1 Function Selection

PINMUX1.SPBK1

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (6) (default)

GPIO: GP[110:105]

McBSP1

McBSP1: CLKX1, FSX1, DX1, CLKR1, FSR1, DR1

Device Configurations

109

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