TNETV2664FIBZWT datasheet(110/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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Table 3-35. Serial Port Sub-Block 1 Function Selection (continued)

PINMUX1.SPBK1

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

McASP0 Transmit with 1 Serializer and

McASP0: AXR0[0], ACLKX0, AFSX0, AHCLKX0,

Mute Control

AMUTEIN0(1), AMUTE0

McBSP1: CLKX1, FSX1, DX1

McBSP1 Transmit, McASP0 SPDIF

McASP0: AXR0[0], AHCLKX0, AMUTE0

(1)

The input from the AMUTEIN0/FSX1/GP[109] pin is connected to both the McASP0 and GPIO.

In addition, the VDD3P3V_PWDN.SP field determines the power state of the Serial Port Block pins. The

Serial Port Block pins default to powered down and not operational. To use these pins, user must first

program VDD3P3V_PWDN.SP = 0 to power up the pins. For more details on the VDD3P3V_PWDN.SP

field, see Section 3.2, Power Considerations.

To facilitate McASP0 operation, the input from the AMUTEIN0/FSX1/GP[109] pin is connected to both the

McASP0 and the GPIO module. Therefore when an external mute event occurs, in addition to notifying the

McASP0, it can also cause an interrupt through the GPIO module.

3.7.3.11 PWM1 Block

This block of 1 pin consists of PWM1 and GPIO muxed pins (GP[4]/PWM1). The PINMUX1.PWM1BK

Table 3-36 summarizes the 1 pin in the PWM1 Block, its multiplexed function, and the PINMUX

configurations to select the corresponding function.

Table 3-36. PWM1 Block Muxed Pin Selection

MULTIPLEXED FUNCTIONS

SIGNAL

PWM1

GPIO

NAME

FUNCTION

SELECT

FUNCTION

SELECT

GP[4]/PWM1

PWM1

PWM1BK = 1

GP[4]

PWM1BK = 0

Table 3-37 provides a different view of the PWM1 Block pin muxing, showing the PWM1 Block function

based on PINMUX1.PWM1BK setting. The selection options are also shown pictorially in Figure 3-10.

Table 3-37. PWM1 Block Function Selection

PINMUX1.PWM1BK

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (1) (default)

GPIO: GP[4]

PWM1

PWM1: PWM1

In addition, the VDD3P3V_PWDN.PWM1 field determines the power state of the PWM1 Block pin. The

PWM1 Block pin defaults to powered down and not operational. To use this pin, user must first program

VDD3P3V_PWDN.PWM1 = 0 to power up the pin. For more details on the VDD3P3V_PWDN.PWM1 field,

see Section 3.2, Power Considerations.

3.7.3.12 CLKOUT Block

This block of 1 pin consists of CLKOUT, PWM2, and GPIO muxed pin (CLKOUT0/PWM2/GP[84]). The

PINMUX1.CKOBK register field selects the pin function in the CLKOUT Block.

Table 3-38 summarizes the 1 pin in the CLKOUT Block, its multiplexed function, and the PINMUX

configurations to select the corresponding function.

110

Device Configurations

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