TNETV2664FIBZWT datasheet(114/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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Table 3-40. EMIFA Block Major Configuration Choices (continued)

MAJOR

PINMUX SELECTION FIELDS

RESULTING PERIPHERALS/PINS

CONFIG.

PCIEN

AEM

RMII

CS3SEL

CS4SEL

CS5SEL

PCI

(1)

EMIFA

(2)

RMII

GPIO

OPTION

PCI:

PGNT, PRST,

PREQ, PINTA,

42 GP pins:

000

PCBE3, PIDSEL

GP[54:52], GP[43:5]

AD31, AD29,

AD27, AD[25:19]

PCI:

PGNT, PRST,

RMII:

34 GP Pins:

PREQ, PINTA,

RMRXER, RMRXD[1:0],

000

GP[54:53], GP[43:34],

PCBE3, PIDSEL

RMTXD[1:0], REFCLK,

GP[26:5]

AD31, AD29,

RMCRSDV, RMTXEN

AD27, AD[25:19]

8-bit EMIFA (NAND) Pinout

Mode 5:

28 GP Pins:

EM_D[7:0], EM_A[2:1],

GP[54:52], GP[43:34],

PCI:

EM_CS2,

GP[31:22], GP[11:10],

PGNT, PRST,

EM_WAIT/(RDY/BSY),

GP[7:5]

PREQ, PINTA,

101

0 or 1

EM_WE, EM_OE

PCBE3, PIDSEL

Optional Selection:

AD31, AD29,

Optional Selection:

GP[33] (CS5SEL = 0),

AD27, AD[25:19]

EM_CS5 (CS5SEL = 1),

GP[32] (CS4SEL = 0),

EM_CS4 (CS4SEL = 1),

GP[13] (CS3SEL = 0)

EM_CS3 (CS3SEL = 1)

8-bit EMIFA (NAND) Pinout

Mode 5:

22 GP Pins:

PCI:

EM_D[7:0], EM_A[2:1],

GP[54:53], GP[43:34],

PGNT, PRST,

RMII:

EM_CS2,

GP[26:22], GP[11:10],

PREQ, PINTA,

RMRXER, RMRXD[1:0],

101

0 or 1

EM_WAIT/(RDY/BSY),

GP[7:5]

PCBE3, PIDSEL

RMTXD[1:0], REFCLK,

EM_WE, EM_OE

AD31, AD29,

RMCRSDV, RMTXEN

Optional Selection:

AD27, AD[25:19]

Optional Selection:

GP[13] (CS3SEL = 0)

EM_CS3 (CS3SEL = 1)

The following is an example on how to read Table 3-40. For example, the "PINMUX Selection Fields" columns indicate that Major Configuration

Choice C is selected through setting PINMUX1.PCIEN = 0, PINMUX0.AEM = 010b, and PINMUX0.RMII = 0. Other PINMUX0 fields CS3SEL,

CS4SEL, and CS5SEL can be set to either 0 or 1 based on the system's EMIFA Chip Select space need. The "Resulting Peripherals/Pins"

columns indicate that Major Configuration Option C can support the following combination of pin functions:

•

No PCI pins

•

Pins for 16-bit EMIFA (Async or NAND) function with EMIFA Chip Select space 2 (EM_CS2). If additional Chip Select spaces are needed, set

the corresponding PINMUX bit (CS5SEL, CS4SEL, and/or CS3SEL) to 1.

•

At least 13 GPIO pins. If the additional Chip Select spaces from EM_CS3, EM_CS4, or EM_CS5 are not needed, the corresponding PINMUX

bit (CS3SEL, CS4SEL, and/or CS5SEL) can be set to 0 to get additional GPIO pins.

3.7.3.13.2 EMIFA Block Pin-By-Pin Multiplexing Summary

This section summarizes the EMIFA Block muxing on a pin-by-pin basis. It provides an alternative view to pin muxing in the EMIFA Block. It

summarizes the EMIFA Block pin muxing by dividing up the EMIFA Block based on the PINMUX field that controls the pins. To determine the

actual EMIFA Major Configuration Option for the application need, see Section 3.7.3.13.1, EMIFA Block Major Configuration Choices.

114

Device Configurations

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