TNETV2664FIBZWT datasheet(115/249 Pages) TI1

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TMS320C6424

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SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Table 3-41 shows the pin multiplexing control for each pin in the EMIFA Sub-Block 0. These PINMUX0 and PINMUX1 register fields control the

multiplexing in this sub-block:

•

PINMUX0: AEM, RMII

•

PINMUX1: PCIEN

Table 3-42 shows the pin multiplexing control for each pin in the EMIFA Sub-Block 1. These PINMUX0 register fields control the multiplexing in

this sub-block:

•

PINMUX0: AEM, CS5SEL, CS4SEL, CS3SEL, RMII

EMIFA Sub-Block 2 is dedicated to EMIFA pins EM_WAIT/(RDY/BSY), EM_OE, and EM_WE. There is no pin multiplexing in this block. These

pins always function as EMIFA control pins.

Table 3-43 shows the pin multiplexing control for each pin in the EMIFA Sub-Block 3. These PINMUX0 and PINMUX1 register fields control the

multiplexing in this sub-block:

•

PINMUX0: AEM

•

PINMUX1: PCIEN

Table 3-41. EMIFA Sub-Block 0 Pin-By-Pin Mux Control

MULTIPLEXED FUNCTIONS

SIGNAL NAME

EMIFA

PCI

EMAC(RMII)

GPIO

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

GP[54]

–

GP[54]

–

GP[53]

–

GP[53]

–

RMRXER/GP[52]

–

RMXER

RMII = 1

GP[52]

RMII = 0

EM_A[13]/AD25/GP[51]

EM_A[13]

PCIEN = 0

AD25

PCIEN = 1

–

GP[51]

PCIEN = 0

AEM = 2

AEM = 0/5

EM_A[14]/AD27/GP[50]

EM_A[14]

AD27

–

GP[50]

EM_A[15]/AD29/GP[49]

EM_A[15]

AD29

–

GP[49]

EM_A[16]/PGNT/GP[48]

EM_A[16]

PGNT

–

GP[48]

EM_A[17]/AD31/GP[47]

EM_A[17]

AD31

–

GP[47]

EM_A[18]/PRST/GP[46]

EM_A[18]

PRST

–

GP[46]

EM_A[19]/PREQ/GP[45]

EM_A[19]

PREQ

–

GP[45]

EM_A[20]/PINTA/GP[44]

EM_A[20]

PINTA

–

GP[44]

Device Configurations

115

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