TNETV2664FIBZWT datasheet(111/249 Pages) TI1

111 / 249 page

TMS320C6424

www.ti.com

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Table 3-38. CLKOUT Block Multiplexed Pin Selection

MULTIPLEXED FUNCTIONS

SIGNAL

CLKOUT0

PWM2

GPIO

NAME

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

CLKOUT0/

PWM2/

CLKOUT0

CKOBK = 01

PWM2

CKOBK = 10

GP[84]

CKOBK = 00

GP[84]

Table 3-39 provides a different view of the CLKOUT Block pin muxing, showing the CLKOUT Block

function based on PINMUX1.CKOBK setting. The selection options are also shown pictorially in

Figure 3-10.

Table 3-39. CLKOUT Block Function Selection

PINMUX1.CKOBK

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (1)

GPIO: GP[84]

CLKOUT (default)

Device Clock-Out: CLKOUT0

PWM2

PWM2: PWM2

Reserved

This block defaults to CLKOUT0 pin function.

In addition, the VDD3P3V_PWDN.CLKOUT field determines the power state of the CLKOUT Block pin.

The CLKOUT Block pin defaults to powered up. For more details on the VDD3P3V_PWDN.CLKOUT field,

see Section 3.2, Power Considerations.

3.7.3.13 EMIFA Block Muxing

This block of 61 pins consists of EMIFA, EMAC(RMII), PCI, and GPIO muxed pins. The following register

fields affect the pin functions in the EMIFA Block:

•

All PINMUX0 register fields: AEM, CS5SEL, CS4SEL, CS3SEL, and RMII.

•

PINMUX1.PCIEN

As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, PCI pins span across the

following Pin Mux Blocks: Host Block, EMIFA Block Sub-Block 0 and Sub-Block 3, PCI Data Block, and

GPIO Block. For proper PCI operation, PCI must be selected in all of these Pin Mux Blocks.

There is only one EMAC peripheral on the C6424 device, even though the pins for MII mode and the pins

for RMII modes are brought out to different locations. The EMAC MII mode pins are in the Host Block,

while EMAC RMII mode pins are only in the EMIFA Block. The user is only allowed to select either the MII

pins or the RMII pins. The operation is undefined if the user attempts to select both MII pins and RMII

pins.

The EMIFA Block is divided into multiple sub-blocks for ultimate flexibility in pin multiplexing to

accommodate a wide variety of applications, and for the purpose of I/O pins power control:

•

Sub-Block 0: multiplexed between EMIFA data/address/control pins, PCI, part of EMAC(RMII), and

GPIO.

•

Sub-Block 1: multiplexed between EMIFA data/address/control pins, part of EMAC(RMII), and GPIO.

•

Sub-Block 2: no multiplexing. EMIFA control pins EM_WAIT/(RDY/BSY), EM_OE, EM_WE.

•

Sub-Block 3: multiplexed between EMIFA address pins EM_A[12:6], PCI, and GPIO.

The EMBK0, EMBK1, EMBK2, EMBK3 fields in the VDD3P3V_PWDN register determine the power state

of the EMIFA Block pins. The EMIFA Block pins default to powered up. For more details on the EMBK0,

EMBK1, EMBK2, EMBK3 fields in the VDD3P3V_PWDN register, see Section 3.2, Power Considerations.

Device Configurations

111

Submit Documentation Feedback

Product Folder Link(s): TMS320C6424

TNETV2664FIBZWT 数据表(PDF) 111 Page - Texas Instruments

TNETV2664FIBZWT 数据表(HTML) 111 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

TNETV2664FIBZWT 数据表(PDF) 111 Page - Texas Instruments

TNETV2664FIBZWT 数据表(HTML) 111 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载