ST7DALIF2 datasheet(169/171 Pages) STMICROELECTRONICS

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ST7DALIF2

Revision history

169/171

19-Nov-2004

Reset delay in section 11.1.3 on page 51 changed to 30 µs

Altered note 1 for section 13.2.3 on page 101 removing references to

RESET

Removed sentence relating to an effective change only after overflow

for CK[1:0], page 60

MOD00 replaced by 0Ex in Figure 36 on page 57

Added Note 2 related to Exit from Active halt, section 11.2.5 on page

Added illegal opcode detection to page 1, section 7.6 on page 29,

section 12 on page 94

Clarification of Flash readout protection, section 4.5.1 on page 14

Added note 4 and description relating to Total Percentage in Error

and Amplifier Output Offset

Variation to the ADC Characteristics subsection and table, page 126

Added note 5 and description relating to Offset Variation in

Temperature to ADC Characteristics subsection and table, page 126

FPLL value of 1MHz quoted as Typical instead of a Minimum in

section 13.3.4.1 on page 104

Updated FSCK in section 13.10.1 on page 121 to fCPU/4 and fCPU/2

Corrected fCPU in Slow and slow wait modes in section 13.4.1 on

page 108

Max values updated for ADC Accuracy, page 124

Notes indicating that PB4 cannot be used as an external interrupt in

HALT mode, section 16.6

on page 138 and Section 8.3 PERIPHERAL INTERRUPTS

Changed section 11.5.2 on page 79

Changed section 11.5.3.3 on page 82

Removed “optional” referring to VDD in Figure 4 on page 13

Changed FMP_R option bit description in section 15.1 on page 130

Added “Clearing active interrupts outside interrupt routine” on page

138

Changed “Development Tools” on page 134

Changed Figure 41 on page 70: fCPU instead of 8 MHz fCPU

Table 100. Document revision history (continued)

Date

Revision

Changes

ST7DALIF2 数据表(PDF) 169 Page - STMicroelectronics

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