ST7DALIF2 datasheet(163/171 Pages) STMICROELECTRONICS

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ST7DALIF2

Device configuration

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OPT3:2 = LVD[1:0] Low voltage detection selection

These option bits enable the LVD block with a selected threshold as shown in Table 97.

OPT1 = WDG SW Hardware or Software

Watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

OPT0 = WDG HALT Watchdog Reset on Halt

This option bit determines if a RESET is generated when entering Halt mode while the

Watchdog is active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

Note:

See Clock Management Block diagram in Figure 12

Table 97.

LVD threshold configuration

Configuration

LVD1

LVD0

LVD Off

Highest Voltage Threshold (

∼4.1V)

Medium Voltage Threshold (

∼3.5V)

Lowest Voltage Threshold (

∼2.8V)

Table 98.

List of valid option combinations

Operating conditions

Option bits

VDD range

Clock source

PLL

Typ fCPU

OSC

PLLOFF PLLx4x8

2.4 V - 3.3 V

Internal RC 1%

off

0.7 MHz @3 V

2.8 MHz @3 V

External clock or

oscillator

(depending on OPT6:4

selection)

off

0-4 MHz

4 MHz

3.3 V - 5.5 V

Internal RC 1%

off

1 MHz @5 V

8 MHz @5 V

External clock or

oscillator

(depending on OPT6:4

selection)

off

0-8 MHz

8 MHz

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