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ST10F296 数据表(PDF) 59 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 59 Page - STMicroelectronics |
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59 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E Internal Flash memory 59/346 Flash non-volatile access protection register 0 (FNVAPR0) Because of the ST10 architecture, the XFlash is seen as external memory. For this reason, it is impossible to access protect it from the real external memory or internal RAM. Flash non-volatile access protection register 1 low (FNVAPR1L) FNVAPR0 (0x0E DFB8) NVR Delivery value: ACFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DBGP ACCP -RW RW Table 30. FNVAPR0 register description Bit Bit name Function 15-2 - Reserved 1DBGP Debug protection This bit, if erased at 1, allows all protections to be by-passed using the debug features through the test interface. If programmed at 0, all the debug features and Flash test modes, and the test interface are disabled. STMicroelectronics will be unable to access the device to run any eventual failure analysis. 0 ACCP Access protection This bit, if programmed at 0, disables any access (read/write) to data mapped inside the IFlash module address space, unless the current instruction is fetched from one of the two Flash modules. FNVAPR1L (0x0E DFBC) NVR Delivery value: FFFFh 15 14 13 12 11 10 987 65432 10 PDS 15 PDS 14 PDS 13 PDS 12 PDS 11 PDS 10 PDS 9 PDS 8 PDS 7 PDS 6 PDS 5 PDS 4 PDS 3 PDS 2 PDS 1 PDS 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 31. FNVAPR1L register description Bit Bit name Function 15-0 PDS[15:0] Protections disable 15-0 If bit PDSx is programmed at 0 and bit PENx (of the FNVAPR1H register) is erased at 1, the ACCP bit action is disabled. Bit PDS0 can be programmed at 0 only if bits DBGP and ACCP (of the FNVAPR0 register) have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0. Obsolete Product(s) - Obsolete Product(s) |
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