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ST10F296 数据表(PDF) 29 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 346 page ![]() Obsolete Product(s) - Obsolete Product(s) ST10F296E Ball data 29/346 XPORT9.0 to XPORT9.15 D15 I/O 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. XPort 9 outputs can be configured as push-pull or open-drain drivers.The input threshold of XPort 9 is selectable (TTL or CMOS). XPORT9.0 C16 I/O XPORT9.1 D14 I/O XPORT9.2 C15 I/O XPORT9.3 B16 I/O XPORT9.4 D13 I/O XPORT9.5 C14 I/O XPORT9.6 B15 I/O XPORT9.7 A15 I/O XPORT9.8 B14 I/O XPORT9.9 C13 I/O XPORT9.10 D12 I/O XPORT9.11 B13 I/O XPORT9.12 C12 I/O XPORT9.13 D11 I/O XPORT9.14 B12 I/O XPORT9.15 XTAL1 A5 I XTAL1: Input to the oscillator amplifier and/or external clock input. XTAL2 A6 O XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC characteristics must be observed RSTIN A3 I Reset input with CMOS Schmitt-Trigger characteristics: A low level at this pin for a specified duration while the oscillator is running resets ST10F296E. An internal pull-up resistor permits power-on reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence. RSTOUT B4 O Internal reset indication output: This pin is driven to a low level during hardware, software or watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. NMI C4 I Non maskable interrupt input: A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = 0 in the SYSCON register, when the PWRDN (power-down) instruction is executed, the NMI pin must be low in order to force the ST10F296E to go into power-down mode. If NMI is high and PWDCFG = 0, when PWRDN is executed, the part will continue to run in normal mode. If not being used, pin NMI should be pulled high externally. XPOUT.0 D4 O XPWM: Channel 0 output XPOUT.1 C3 O XPWM: Channel 1 output XPOUT.2 B2 O XPWM: Channel 2 output XPOUT.3 C2 O XPWM: Channel 3 output XADCINJ L3 O Output trigger for ADC channel injection Table 2. Ball description (continued) Symbol Ball no. Type Function (including port, pin and alternate function where applicable) Obsolete Product(s) - Obsolete Product(s) |
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