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ST10F296 数据表(PDF) 15 Page - STMicroelectronics

部件名 ST10F296
功能描述  High performance 16-bit CPU with DSP functions
PDF  346 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F296 数据表(HTML) 15 Page - STMicroelectronics

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Figure 49.
Port 6 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 50.
Block diagram of Port 6 pins 7, 6, 1, 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 51.
Block diagram of pin P6.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 52.
Block diagram of pins P6.2, P6.3, and P6.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 53.
Port 7 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 54.
Block diagram of Port 7 pins 3 to 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 55.
Block diagram of Port 7 pins 7 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 56.
Port 8 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 57.
Block diagram of P8 pins 5 to 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 58.
Block diagram of pin P8.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 59.
Block diagram of pin P8.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 60.
XPort 10 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 61.
Block diagram of an XPort 10 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 62.
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 63.
XTimer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 64.
Asynchronous mode of serial channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 65.
Synchronous mode of serial channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 66.
Synchronous serial channel SSC0 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 67.
Connection to a single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . 194
Figure 68.
Connection to a single CAN bus via common CAN transceivers . . . . . . . . . . . . . . . . . . . 194
Figure 69.
Connection to two different CAN buses (example for gateway application) . . . . . . . . . . . 195
Figure 70.
Connection to one CAN bus with internal parallel mode enabled. . . . . . . . . . . . . . . . . . . 195
Figure 71.
ESFRs and port pins associated with the RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 72.
RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 73.
Prescaler registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 74.
Divider counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 75.
Asynchronous power-on reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 76.
Asynchronous power-on reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 77.
Asynchronous hardware reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 78.
Asynchronous hardware reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 79.
Synchronous short/long hardware reset (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 80.
Synchronous short/long hardware reset (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 81.
Synchronous long hardware reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 82.
Synchronous long hardware reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 83.
Software/watchdog timer unidirectional reset (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 84.
Software/watchdog timer unidirectional reset (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 85.
Software/watchdog timer bidirectional reset (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 86.
Software/watchdog timer bidirectional reset (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 87.
Software/watchdog timer bidirectional reset (EA = 0) followed by a hardware reset . . . . 232
Figure 88.
Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 89.
System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 90.
Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 235
Figure 91.
Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 236
Figure 92.
Port 0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 93.
External RC circuit on the RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 94.
Simplified power-down exit circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 95.
Power-down exit sequence when using an external interrupt (PLL x 2) . . . . . . . . . . . . . . 243
Figure 96.
Port 2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 97.
Supply current versus the operating frequency (run and idle modes) . . . . . . . . . . . . . . . 299
Figure 98.
AD conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 99.
ADC input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 100. Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 307
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