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ST10F296 数据表(PDF) 33 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 33 Page - STMicroelectronics |
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33 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E Memory organization 33/346 4 Memory organization The memory space of the ST10F296E is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 Mbytes. The entire memory space can be accessed byte wise or word wise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The organization of the ST10F296E memory is described in the sections below and shown in Figure 4: ST10F296E on-chip memory mapping on page 38. 4.1 IFlash IFlash comprises 512 Kbytes of on-chip Flash memory. It is divided into 10 blocks (B0F0...B0F9) of Bank 0, and two blocks of Bank 1 (B1F0, B1F1). Read-while-write operations inside the same bank are not allowed. When bootstrap mode is selected, the Test-Flash Block B0TF (8 Kbyte) appears at address 00’0000h. Refer to Section 5: Internal Flash memory on page 42 for more details on memory mapping in boot mode. The summary of address ranges for IFlash is given in Table 3. Table 3. Address ranges for IFlash Blocks User mode Size (Kbytes) B0TF Not visible 8 B0F0 00’0000h - 00’1FFFh 8 B0F1 00’2000h - 00’3FFFh 8 B0F2 00’4000h - 00’5FFFh 8 B0F3 00’6000h - 00’7FFFh 8 B0F4 01’8000h - 01’FFFFh 32 B0F5 02’0000h - 02’FFFFh 64 B0F6 03’0000h - 03’FFFFh 64 B0F7 04’0000h - 04’FFFFh 64 B0F8 05’0000h - 05’FFFFh 64 B0F9 06’0000h - 06’FFFFh 64 B1F0 07’0000h - 07’FFFFh 64 B1F1 08’0000h - 08’FFFFh 64 Obsolete Product(s) - Obsolete Product(s) |
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