ST10F296 datasheet(75/346 Pages) STMICROELECTRONICS

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ST10F296E

The bootstrap loader

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6.3.3

ST10 configuration in UART BSL (RS232 or K-line)

When the ST10F296E has entered BSL mode on the UART, the configuration shown in

Table 37 is automatically set (values that deviate from the normal reset values, are

highlighted in bold italic).

The watchdog timer is disabled, except after a normal reset, so the bootstrap loading

sequence is not time limited. Pin TxD0 is configured as output, so the ST10F296E can

return the acknowledge byte. Even if the internal IFlash is enabled, no code can be

executed out of it.

6.3.4

Loading the startup code

After sending the acknowledge byte the BSL enters a loop to receive 32 bytes via ASC0.

These bytes are stored sequentially into locations 00’FA40H through 00’FA5FH of the IRAM.

Up to 16 instructions may be placed into the RAM area. To execute the loaded code the BSL

jumps to location 00’FA40H, i.e. the first loaded instruction. The bootstrap loading sequence

then terminates, however, the ST10F296E remains in BSL mode. It is likely that the initially

loaded routine loads additional code or data, as an average application is likely to require

substantially more than 16 instructions. This second receive loop may directly use the pre-

initialized interface ASC0 to receive data and store it to arbitrary user-defined locations.

This second level of loaded code may be the final application code. It may also be another,

more sophisticated, loader routine that adds a transmission protocol to enhance the integrity

of the loaded code or data. In addition, it may contain a code sequence to change the

system configuration and enable the bus interface to store the received data into the

external memory.

Table 37.

ST10 configuration in UART BSL mode (RS232 or K-line)

Watchdog timer

Disabled

0400H

(1)

In bootstrap modes (standard or alternate) the ROMEN bit, bit 10 of the SYSCON register, is always set

regardless of the EA pin level. The BYTDIS bit, bit 9 of the SYSCON register, is set according to the data

bus width selection via Port 0 configuration.

Context pointer CP

FA00H

Stack pointer SP

FA40H

FC00H

Acc. to startup

config.(2)

BUSCON0 is initialized with 0000h which disables the external bus if pin EA is high during reset. If pin EA

is low during reset, the BUSACT0 bit, bit 10, and the ALECTL0 bit, bit 9, are set, enabling the external bus

with a lengthened ALE signal. BTYP field, bit 7 and 6, is set according to Port 0 configuration.

8011H

Initialized only if bootstrap is run via UART

Acc. to 00 byte

Initialized only if Bootstrap is run via UART

P3.10/TXD0

Initialized only if Bootstrap is run via UART

DP3.10

Initialized only if Bootstrap is run via UART

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