ST10F296 datasheet(49/346 Pages) STMICROELECTRONICS

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ST10F296E

Internal Flash memory

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DWPG

Double word program

This bit must be set to select the double word (64 bits) program operation in

the Flash modules. The double word program operation allows 0s to be

programmed instead of 1s. The Flash address in which to program (aligned

with even words) must be written in the FARH/L registers, while the two

Flash data to be programmed must be written in the FDR0H/L registers

(even word) and FDR1H/L registers (odd word) before starting the

execution by setting the WMS bit. The DWPG bit is automatically reset at

the end of the double word program operation.

SER

Sector erase

This bit must be set to select the sector erase operation in the Flash

modules. The sector erase operation allows all Flash locations to 0xFF to

be erased. 1 to all sectors of the same bank (excluding the Test-Flash for

Bank B0) can be erased through bits BxFy of the FCR1H/L registers before

starting the execution by setting the WMS bit. Preprogramming the sectors

to 0x00 is done automatically. The SER bit is automatically reset at the end

of the sector erase operation.

10-9

Reserved

SPR

Set protection

This bit must be set to select the set protection operation. The set

protection operation allows 0s to be programmed instead of 1s in the Flash

non-volatile protection registers. The Flash address in which to program

must be written in the FARH/L registers, while the Flash data to be

programmed must be written in the FDR0H/L before starting the execution

by setting the WMS bit. A sequence error is flagged by the SEQER bit of

the FER register if the address written in FARH/L is not in the range

0x0EDFB0-0x0EDFBF. The SPR bit is automatically reset at the end of the

set protection operation.

7SMOD

Select module

If this bit is reset, a write operation is performed on the XFlash module. if

this bit is set, a write operation is performed on IFlash module. The SMOD

bit is automatically reset at the end of the write operation.

6-0

Reserved

Table 12.

FCR0H register decription (continued)

Bit

Bit name

Function

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