ST10F296 datasheet(37/346 Pages) STMICROELECTRONICS

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ST10F296E

Memory organization

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4.12

I2C

Address range 00’EA00h - 00’EAFFh is reserved for the I2C module access. The I2C is

enabled by setting the XPEN bit (bit 2 of the SYSCON register) and bit 9 of the XPERCON

word access is possible). Two waitstates give an access time of 62.5 ns at 64 MHz CPU

clock. No tristate waitstate is used.

4.13

XTimer/XMiscellaneous

Address range 00’EB00h - 00’EB7Fh is reserved for the access to XTimer and to a set of

XBus additional features (XMiscellaneous). They are enabled by setting the XPEN bit (bit 2

of the SYSCON register) and bit 10 of the XPERCON register. Access to these additional

modules and features use demultiplexed addresses and a 16-bit data bus (only word access

is possible). Two waitstates give an access time of 62.5 ns at 64 MHz CPU clock. No tristate

waitstate is used. In addition to the XTimer module control registers, the following set of

features are provided:

●

CLKOUT programmable divider

●

XBus interrupt management registers

●

ADC multiplexing on the P1L register

●

Port 1L digital disable register for extra ADC channels

●

CAN2 multiplexing on P4.5/P4.6

●

CAN1-2 main clock prescaler

●

Main voltage regulator disable for power-down mode

●

TTL/CMOS threshold selection for Port 0, Port 1, Port 5, XPort 9 and XPort 10.

4.14

XPort 9/XPort 10

Address range 00’EB80h - 00’EBFFh is reserved for access to XPort 9 and XPort 10. They

are enabled by setting the XPEN bit (bit 2 of the SYSCON register) and bit 11 of the

XPERCON register. These additional modules are accessed by demultiplexed addresses

and a 16-bit data bus (only word access is possible). Two waitstates give an access time of

62.5 ns at 64 MHz CPU clock. No tristate waitstate is used.

4.15

Visibility of XBus peripherals

To retain compatibility between the ST10F296E and the ST10F280, the XBus peripherals

can be selected to be visible and/or accessible on the external address/data bus. Different

bits must be set in the XPERCON register to enable the XPeripherals. If these bits are

cleared before global enabling with the XPEN bit (in the SYSCON register), the

corresponding address space, port pins and interrupts are not occupied by the peripherals,

and the peripheral is not visible and not available. Refer to Section 23: Register set on

page 248.

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