ST10F296 datasheet(41/346 Pages) STMICROELECTRONICS

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Memory organization

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In emulation mode, all XPeripherals are enabled (all XPERCON bits are set). The access to

the external memory and/or the XBus is controlled by the bondout chip.

Reserved bits of the XPERCON register must always be written to 0.

When the RTC is disabled (RTCEN = 0) the main clock oscillator is switched off if the ST10

enters power-down mode. When the RTC is enabled, the RTCOFF bit of the RTCCON

Section 18: Real-time clock (RTC) on page 203).

Table 6 summarizes the address range mapping on segment 8 for programming the

ROMEN and XPEN bits (of the SYSCON register) and the XRAM2EN and XFLASHEN bits

(of the XPERCON register).

XPEREMU register

The XPEREMU register is a write-only register that is mapped on the XBus memory space

at address EB7Eh. It contrasts with the XPERCON register, a read/write ESFR register,

which must be programmed to enable the single XBus modules separately.

Once the XPEN bit of the SYSCON register is set and at least one of the XPeripherals

(except the memories) is activated, the XPEREMU register must be written with the same

content as the XPERCON register. This is to allow a correct emulation of the new set of

features introduced on the XBus for the new ST10 generation. The following instructions

must be added inside the initialization routine:

if (SYSCON.XPEN && (XPERCON & 0x07D3))

then { XPEREMU = XPERCON }

XPEREMU must be programmed after both the XPERCON and SYSCON registers in such

a way that the final configuration for the XPeripherals is stored in the XPEREMU register

and used for the emulation hardware setup.

XPEREMU bit descriptition follows the XPERCON register (see Table 5: XPERCON register

description on page 39).

Table 6.

Segment 8 address range mapping

ROMEN

XPEN

XRAM2EN

XFLASHEN

Segment 8

x(1)

External memory

x(1)

Reserved

x(1)

Reserved

1x(1)

Don’t care

x(1)

IFlash (B1F1)

XPEREMU (EB7Eh)

XBus

Reset value: xxxxh

XPORT

XMISC

XI2C

XSSC

XASC

XPWM

XFLASH

XRTC

XRAM

2EN

XRAM

1EN

CAN

2EN

CAN

1EN

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