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ST10F296 数据表(PDF) 26 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 26 Page - STMicroelectronics |
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26 / 346 page  Obsolete Product(s) - Obsolete Product(s) Ball data ST10F296E 26/346 P4.0 to P4.7 N16 O 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold is selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured as push-pull or open-drain drivers. In case of an external bus configuration, Port 4 can be used to output the segment address lines. P4.0 A16 Least significant segment address line M15 O P4.1 A17 Segment address line L14 O P4.2 A18 Segment address line M16 O P4.3 A19 Segment address line L15 O P4.4 A20 Segment address line I CAN2_RxD CAN2: Receive data input I/O SCL I2C interface: Serial clock L16 O P4.5 A21 Segment address line I CAN1_RxD CAN1: Receive data input I CAN2_RxD CAN2: Receive Data Input K14 O P4.6 A22 Segment address line O CAN1_TxD CAN1: Transmit data output O CAN2_TxD CAN2: Transmit data output K15 O P4.7 A23 Most significant segment address line O CAN2_TxD CAN2: Transmit data output I/O SDA I2C interface: Serial data RD J14 O External memory read strobe: RD is activated for every external instruction or data read access. WR and WRL J15 O External memory write strobe: In WR mode this pin is activated for every external data write access. In WRL mode this pin is activated for low byte data write access on a 16- bit bus, and, for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. READY and READY J16 I Ready input: The active level is programmable. When the Ready function is enabled, the selected inactive level at this pin during an external memory access forces the insertion of memory cycle time waitstates until the pin returns to the selected active level. ALE J17 O Address latch enable output: Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA and VSTBY H17 I External access enable pin: A low level applied to this pin during and after reset forces the ST10F296E to start the program from the external memory space. A high level forces ST10F296E to start in the internal memory space. This pin is also used (when standby mode is entered: ST10F296E under reset and main VDD turned off) to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8 V supply to retain data inside the standby portion of the XRAM (16 Kbyte). It can range from 4.5 to 5.5 V (6 V for a reduced amount of time during the device life). In running mode, this pin can be tied low during reset without affecting XRAM activities, since the presence of a stable VDD guarantees the proper biasing of this module. Table 2. Ball description (continued) Symbol Ball no. Type Function (including port, pin and alternate function where applicable) Obsolete Product(s) - Obsolete Product(s) |
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