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ST10F296 数据表(PDF) 82 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 346 page ![]() Obsolete Product(s) - Obsolete Product(s) The bootstrap loader ST10F296E 82/346 6.4.5 Choosing the baud rate for the BSL via CAN The bootstrap via CAN acts in the same way as the UART bootstrap mode. When the ST10F296E is started in BSL mode, it polls the RxD0 and CAN1_RxD lines. When polling a low level on one of these lines, a timer is launched that is stopped when the line goes back to high level. For CAN communication, the algorithm is made to receive a zero frame, where the standard identifier is 0x0 and DLC is 0. This frame produces the following levels on the network: 5D, 1R, 5D, 1R, 5D, 1R, 5D, 1R, 5D, 1R, 4D, 1R, 1D, 11R. The algorithm lets the timer run until detection of the 5th recessive bit. In this way, the bit timing is calculated over 29 bit time durations. This minimizes the error introduced by the polling. Figure 13. Bit rate measurement over a predefined zero-frame Error induced by the polling The code used for polling is as follows: WaitCom: JNB P4.5,CAN_Boot ; if SOF detected on CAN, then go to CAN ; loader JB P3.11,WaitCom ; Wait for start bit at RxD0 BSET T6R ; Start Timer T6 .... CAN_Boot: BSET PWMCON0.0 ; Start PWM Timer0 ; (resolution is 1 CPU clk cycle) JMPR cc_UC,WaitRecessiveBit WaitDominantBit: JB P4.5,WaitDominantBit ; wait for end of stuff bit WaitRecessiveBit: JNB P4.5,WaitRecessiveBit ; wait for 1st dominant bit = Stuff bit CMPI1 R1,#5 ; Test if 5th stuff bit detected JMPR cc_NE,WaitDominantBit ; No, go back to count more BCLR PWMCON.0 ; Stop timer ; here the 5th stuff bit is detected: ; PT0 = 29 Bit_Time (25D and 4R) The maximum error at detection of communication on the CAN pin is: (1 not taken + 1 taken jumps) + 1 taken jump + 1 bit set: (6) + 6 CPU clock cycles The error at detection of the 5th recessive bit is: (1 taken jump) + 1 not taken jump + 1 compare + 1 bit clear: (4) + 6 CPU cycles In the worst case scenario, the induced error is 6 CPU clock cycles. So, polling could induce an error of 6 timer ticks. ........ Start Stuff bit Stuff bit Stuff bit Stuff bit Measured time Obsolete Product(s) - Obsolete Product(s) |
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