ST10F296 datasheet(71/346 Pages) STMICROELECTRONICS

71 / 346 page

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ST10F296E

The bootstrap loader

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Figure 8.

Hardware provisions to activate the BSL

6.2.5

Memory configuration in bootstrap loader mode

The configuration (i.e. the accessibility) of the ST10F296E’s memory areas after reset in

bootstrap loader mode differs from the standard case. Pin EA is evaluated when BSL mode

is selected to enable the external bus or not:

●

If EA = 1, the external bus is disabled (BUSACT0 = 0 in BUSCON0 register);

●

If EA = 0, the external bus is enabled (BUSACT0 = 1 in BUSCON0 register).

Moreover, while in BSL mode, access to the internal IFlash area are partly redirected:

●

Code access is made from the special Test-Flash seen in the range 00’0000h to

00’01FFFh.

●

User IFlash is only available for read and write access (Test-Flash cannot be read nor

written).

●

Write access must be made with addresses starting in segment 1 from 01'0000h,

whatever the value of the ROMS1 bit in the SYSCON register.

●

Read access is made in segment 0 or in segment 1 depending on the ROMS1 bit

value.

●

In BSL mode, by default, ROMS1= 0 so the first 32 Kbytes of IFlash are mapped in

segment 0.

Example

In default configuration, to program address 0, the user must put the value 01'0000h in the

FARL and FARH registers. However, to verify the content of the address 0 a read to

00'0000h must be performed.

Figure 9 shows the memory configuration after reset.

RP0L.4

Ω max.

Circuit 1

P0L.4

Normal Boot

BSL

External

Signal

RP0L.4

Ω max.

Circuit 2

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