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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST10F296 数据表(PDF) 74 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 74 Page - STMicroelectronics |
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74 / 346 page  Obsolete Product(s) - Obsolete Product(s) The bootstrap loader ST10F296E 74/346 Figure 10. UART bootstrap loader sequence 1. BSL initialization time > 1ms @ fCPU = 40 MHz. 2. Zero byte (1 start bit, eight 0 data bits, 1 stop bit), sent by host. 3. Acknowledge byte, sent by ST10F296E. 4. 32 bytes of code / data, sent by host. 5. TxD0 is only driven a certain time after reception of the zero byte (1.3 ms @ fCPU = 40 MHz). 6. Internal boot ROM / Test-Flash. 6.3.2 Entering bootstrap via UART The ST10F296E enters BSL mode at the end of a hardware reset if pin P0L.4 is sampled low. In this case, the built-in bootstrap loader is activated independent of the selected bus mode. The bootstrap loader code is stored in a special Test-Flash, for which no part of the standard mask ROM or Flash memory area is required. After entering BSL mode and the respective initialization, the ST10F296E scans the RxD0 line to receive a zero byte (one start bit, eight 0 data bits and one stop bit). From this zero byte, it calculates the corresponding baud rate factor with respect to the current CPU clock, initializes the serial interface ASC0 accordingly, and switches the TxD0 pin to output. Using this baud rate, an acknowledge byte is returned to the host that provides the loaded data. The acknowledge byte for the ST10F296E is D5h. RSTIN TxD0 Int. boot ROM/Test-Flash BSL-routine 32 bytes 2) 3) RxD0 CSP:IP user software 4) 6) P0L.4 1) 5) Obsolete Product(s) - Obsolete Product(s) |
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