ST10F296 datasheet(46/346 Pages) STMICROELECTRONICS

46 / 346 page

Obsolete

Product(s)

- Obsolete

Product(s)

Internal Flash memory

ST10F296E

46/346

During a Flash write operation any attempt to read the bank under modification outputs

invalid data (software trap 009Bh). This means that the Flash bank is not fetchable when a

write operation is active. The write operation commands must be executed from another

bank, from the other module or from another memory (internal RAM or external memory).

Note:

During a write operation, when the LOCK bit of the FCR0 register is set, it is forbidden to

write into the Flash control registers.

5.2.1

Power supply drop

If, during a write operation, the internal low voltage supply drops below a certain internal

voltage threshold, any write operation that is running is suddenly interrupted and the

modules are reset to read mode. Following power-on, an interrupted Flash write operation

must be repeated.

5.3

Internal Flash memory registers

Flash control register 0 low (FCR0L)

The Flash control register 0 low (FCR0L) together with the Flash control register 0 high

(FCR0H) is used to enable and to monitor all the write operations for both Flash modules.

The user has no access in write mode to the Test-Flash (B0TF). The Test-Flash block is only

seen by the user in bootstrap mode.

FCR0L (0x0E 0000)

FCR

Reset value: 0000h

Reserved

BSY1 BSY0 LOCK Res.

BSY3 BSY2 Res.

-R

Table 11.

FCR0L register decription

BIt

Bit name

Function

15-7

Reserved

6-5

BSY[1:0]

Bank 1:0 busy (IFlash)

These bits indicate that a write operation is running in the

corresponding bank of IFlash. They are automatically set when the

WMS bit of the FCR0H register is set. When the BSY [1:0] bits are set

every read access to the corresponding bank outputs invalid data

(software trap 009Bh), while every write access to the bank is ignored.

At the end of a write operation or during a program or erase suspend

these bits are automatically reset and the bank returns to read mode.

After a program or erase resume these bits are automatically reset.

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296 数据表(PDF) 46 Page - STMicroelectronics

ST10F296 数据表(HTML) 46 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ST10F296 数据表(PDF) 46 Page - STMicroelectronics

ST10F296 数据表(HTML) 46 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载