ST10F296 datasheet(35/346 Pages) STMICROELECTRONICS

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Memory organization

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4.4

Extension RAM (XRAM)

64 Kbyte and 2 Kbytes of on-chip XRAM (single port XRAM) is provided as a storage for

data, user stack and code.

The XRAM is divided into 2 areas, the first 2 kbytes and second 64 Kbytes, called XRAM1

and XRAM2 respectively, are connected to the internal XBus and are accessed like an

external memory in 16-bit demultiplexed bus-mode without wait state or read/write delay

(31.25 ns access at 64 MHz CPU clock). Byte and word access is allowed.

The XRAM1 address range is 00’E000h - 00’E7FFh if the XPEN bit (bit 2 of the SYSCON

XPEN bits are cleared, any access in the address range 00’E000h - 00’E7FFh is directed to

external memory interface, using the BUSCONx register corresponding to an address

matching the ADDRSELx register.

The XRAM2 address range is 0F’0000h - 0F’FFFFh if the XPEN bit and XRAM2EN bit (bit 3

of the XPERCON register) are set. If the XRAM2EN or XPEN bits are cleared, any access in

the address range 00’C000h - 00’DFFFh is directed to the external memory interface, using

the BUSCONx register corresponding to an address matching the ADDRSELx register. The

same thing happens when the XPEN bit is set, but both the XRAM2EN and XFLASHEN bits

are cleared.

The lower 16 Kbyte portion of XRAM2 (address range 0F’0000h-0F’3FFFh) represents the

standby RAM which can be maintained biased through EA / VSTBY pin when the main

supply VDD is turned off.

As the XRAM appears as external memory, it cannot be used as a system stack or as a

addressable.

Note:

When the ROMEN bit in the SYSCON register is low, and the XPEN bit is set, and at least

one of the two bits XFLASHEN or XRAM2EN in the XPERCON register are also set, the

address 08’0000h - 08’FFFFh must be reserved (no external memory access is enabled).

4.5

Special function register (SFR) areas

An area of 1024 bytes (2 x 512 bytes) of address space is reserved for special function

registers (SFR) and extended special function registers (ESFR). SFRs are wordwide

registers which are used to control and to monitor the function of the different on-chip units.

4.6

CAN1

Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 module access. CAN1 is

enabled by setting the XPEN bit (bit 2 of the SYSCON register) and the CAN1EN bit (bit 0 of

the XPERCON register). Access to the CAN module use demultiplexed addresses and a 16-

bit data bus (only word access is possible). Two wait states give an access time of 62.5 ns at

64 MHz CPU clock. No tristate wait states are used.

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