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ST10F296 数据表(PDF) 97 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E External bus controller (EBC) 97/346 8 External bus controller (EBC) All external memory access is performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes: ● 16-/18-/20-/24-bit addresses and 16-bit data, demultiplexed ● 16-/18-/ 20-/24-bit addresses and 16-bit data, multiplexed ● 16-/18-/20-/24-bit addresses and 8-bit data, multiplexed ● 16-/18-/20-/24-bit addresses and 8-bit data, demultiplexed In demultiplexed bus modes addresses are output on Port 1 and data is input/output on Port 0 or P0L, respectively. In the multiplexed bus modes both addresses and data use Port 0 for input/output. Timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ALE and read/write delay) are programmable giving the choice of a wide range of memories and external peripherals. Up to four independent address windows may be defined (using register pairs ADDRSELx/BUSCONx) to access different resources and bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. Access to locations not covered by these four address windows is controlled by BUSCON0. Up to five external CS signals (four windows plus default) can be generated to save external glue logic. Access to very slow memories is supported by a ‘ready’ function. A HOLD/HLDA protocol is available for bus arbitration which shares external resources with other bus masters. The bus arbitration is enabled by setting the HLDEN bit in the PSW register. After setting HLDEN once, pins P6.7 to P6.5 (BREQ, HLDA, and HOLD) are automatically controlled by the EBC. In master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to 1, slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic. For applications which require less external memory space, the address space can be restricted to 1 Mbyte, 256 Kbytes or to 64 Kbytes. Port 4 outputs all eight address lines if an address space of 16 Mbytes is used, otherwise four, two or no address lines. Chip select timing can be made programmable. By default (after reset), the CSx lines change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON register, the CSx lines change with the rising edge of ALE. The active level of the READY pin can be set by the RDYPOL bit in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by the RDYPOL bit in the associated BUSCON register. Obsolete Product(s) - Obsolete Product(s) |
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