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ST10F296 数据表(PDF) 17 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E Description 17/346 1 Description The ST10F296E is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 32 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via the phase-locked loop (PLL). ST10F296E is processed in 0.18 µm CMOS technology. The MCU core and the logic is supplied with a 5 V to 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V supply and I/Os work at 5 V. The device is upwardly compatible with the ST10F280 device, with the following differences: ● The Flash control interface is now based on STMicroelectronics third generation of standalone Flash memories (M29F400 series), with an embedded program/erase controller. This completely frees up the CPU during programming or erasing of the Flash. ● Pins DC1 and DC2 of ST10F280, are renamed as V18. Do not connect these pins to 5.0 V external supply. Instead, these pin should be connected to a decoupling capacitor (ceramic type, typical value 10 nF, maximum value 100 nF). ● The AC and DC parameters are modified due to a difference in the maximum CPU frequency. ● The EA pin has assumed a new, alternate functionality: It is also used to provide a dedicated power supply (see VSTBY) to maintain a portion of the XRAM (16 Kbytes) biased when the main power supply of the device (VDD and consequently the internally generated V18) is turned off for low power mode, thereby allowing data retention. VSTBY voltage is in the range 4.5-5.5 V, and a dedicated embedded low power voltage regulator provides the 1.8 V for the RAM. The upper limit of up to 6 V may be exceeded for a very short period of time during the global life of the device. The lower limit of 4 V may also be exceeded. ● A second SSC, mapped on the XBus, has been added (SSC of ST10F280 becomes SSC0, while the new SSC is referred to as XSSC or SSC1). There are some restrictions and functional differences due to peculiarities present in the XBus between the classic SSC and the new XSSC. ● A second ASC, mapped on the XBus, has been added (ASC0 of ST10F280 remains ASC0, while the new one is referred to as XASC or ASC1). Some restrictions and functional differences due to peculiarities present in the XBus between the classic ASC, and the new XASC. ● The second PWM (XPWM), mapped on the XBus, has been improved adding set/clear command for safe management of the control register. Memory mapping is thus slightly different. ● An I2C interface on the XBus has been added (see X-I2C or simply I2C interface). ● The CLKOUT function can output either the CPU clock (as in ST10F280) or a software programmable prescaled value of the CPU clock. ● the embedded memory size has been significantly increased (both Flash and RAM). ● PLL multiplication factors have been adapted to new frequency range. Obsolete Product(s) - Obsolete Product(s) |
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