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ST10F296 数据表(PDF) 93 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 93 Page - STMicroelectronics |
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93 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E Central processing unit (CPU) 93/346 7.1 Multiplier-accumulator unit (MAC) The specialized MAC coprocessor has been added to the ST10 CPU core to improve the computing performances of the ST10 device during signal processing tasks. The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new coprocessor with up to two operands per instruction cycle. This new MAC coprocessor contains a fast multiply-accumulate unit and a repeat unit. The coprocessor instructions extend the ST10 CPU instruction set with multiply, multiply- accumulate, and 32-bit signed arithmetic operations. Figure 17. MAC unit architecture 1. Shared with standard ALU Operand 2 Operand 1 Control unit Repeat unit ST10 CPU Interrupt controller MSW MRW MAH MAL MCW Flags MAE Mux 8-bit left/right shifter Mux Mux Sign extend 16 x 16 Concatenation signed/unsigned multiplier 40-bit signed arithmetic unit 0h 0h 08000h 40 16 40 40 32 32 16 40 40 40 40 40 Scaler AB 40 GPR pointers(1) IDX0 pointer IDX1 pointer QR0 GPR offset register QR1 GPR offset register QX0 IDX offset register QX1 IDX offset register Obsolete Product(s) - Obsolete Product(s) |
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