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ST10F296 数据表(PDF) 42 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 42 Page - STMicroelectronics |
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42 / 346 page  Obsolete Product(s) - Obsolete Product(s) Internal Flash memory ST10F296E 42/346 5 Internal Flash memory The on-chip Flash is composed of two matrix modules each one containing one array divided into two banks that can be read and modified independently of the other (i.e. one bank can be read while the other is under modification). Figure 5. Flash modules structure The write operations of the four banks are managed by an embedded Flash program/erase controller (FPEC). The high voltages needed for program/erase operations are internally generated. The data bus is 32 bits wide. Due to ST10 core architecture limitations, only the first 512 Kbytes are accessed at 32-bit (internal Flash bus, also known as IBus), while the remaining 320 Kbytes are accessed at 16-bit (also known as XBus). 5.1 Functional description 5.1.1 Structure Table 7 shows the address space reserved for the Flash module. . Bank 1: 128 Kbyte Bank 0: 384 Kbyte Program Memory HV and Ref. Generator Program/Erase Controller I-BUS Interface + 8 Kbyte Test-Flash Bank 3: 128 Kbyte Bank 2: 192 Kbyte Program Memory XFLASH (Module X) X-BUS Interface IFLASH (Module I) Control Section Program Memory Program Memory Table 7. Flash module absolute mapping Description Addresses Size (Kbytes) IFlash sectors 0x00 0000 to 0x08 FFFF 512 XFlash sectors 0x09 0000 to 0x0D FFFF 320 Registers and Flash internal reserved area 0x0E 0000 to 0x0E FFFF 64 Obsolete Product(s) - Obsolete Product(s) |
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