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ST10F296 数据表(PDF) 68 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 68 Page - STMicroelectronics |
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68 / 346 page  Obsolete Product(s) - Obsolete Product(s) The bootstrap loader ST10F296E 68/346 6.2.2 ST10 configuration in BSL When the ST10F296E has entered BSL mode, the configuration shown in Table 36 is automatically set (values that deviate from the normal reset values, are highlighted in bold italic). . Table 36. ST10 configuration in BSL mode Watchdog timer Disabled Register SYSCON 0404H (1) 1. In bootstrap modes (standard or alternate) the ROMEN bit, bit 10 of the SYSCON register, is always set regardless of the EA pin level. The BYTDIS bit, bit 9 of the SYSCON register, is set according to the data bus width selection via Port 0 configuration. XPEN bit set for bootstrap via CAN or alternate boot mode Context pointer CP FA00H Register STKUN FC00H Stack pointer SP FA40H Register STKOV FA00H Register BUSCON0 Acc. to startup config.(2) 2. BUSCON0 is initialized with 0000h which disables the external bus if pin EA is high during reset. If pin EA is low during reset, the BUSACT0 bit, bit 10, and the ALECTL0 bit, bit 9, are set, enabling the external bus with a lengthened ALE signal. BTYP field, bit 7 and 6, is set according to Port 0 configuration. Register S0CON 8011H Initialized only if bootstrap is run via UART Register S0BG Acc. to ‘00’ byte Initialized only if bootstrap is run via UART P3.10/TXD0 1 Initialized only if bootstrap is run via UART DP3.10 1 Initialized only if bootstrap is run via UART CAN1 status/control register 0000H Initialized only if bootstrap is run via CAN CAN1 bit timing register Acc. to 0 frame Initialized only if bootstrap is run via CAN XPERCON 042DH XRAM1-2, XFlash, CAN1 and XMISC enabled. Initialized only if bootstrap is run via CAN P4.6/CAN1_TxD 1 Initialized only if bootstrap is run via CAN DP4.6 1 Initialized only if bootstrap is run via CAN Obsolete Product(s) - Obsolete Product(s) |
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