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ST10F296 数据表(PDF) 100 Page - STMicroelectronics |
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ST10F296 数据表(HTML) 100 Page - STMicroelectronics |
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100 / 346 page  Obsolete Product(s) - Obsolete Product(s) Interrupt system ST10F296E 100/346 9 Interrupt system The interrupt response time for internal program execution is from 78 ns to 187.5 ns at 64 MHz CPU clock. The ST10F296E architecture supports several mechanisms for fast, flexible responses to service requests that can be generated from various sources (internal or external) to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt controller or by the peripheral event controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F296E has eight PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. An interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit-field is dedicated to each existing interrupt source. Because of its related register, each source can be programmed to one of sixteen interrupt priority levels. Once processing by the CPU starts, an interrupt service can only be interrupted by a higher prioritized service request. For standard interrupt processing, each possible interrupt sources has a dedicated vector location. Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Fast external interrupts may also have interrupt sources selected from other peripherals. For example, the CANx controller receive signals (CANx_RxD) and I2C serial clock signal can be used to interrupt the system. Table 47 shows all the available ST10F296E interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. Obsolete Product(s) - Obsolete Product(s) |
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